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    DIE-TO-DIE INTERCONNECT
    1.
    发明申请
    DIE-TO-DIE INTERCONNECT 有权

    公开(公告)号：US20220342840A1

    公开(公告)日：2022-10-27

    申请号：US17852865

    申请日：2022-06-29

    申请人： Intel Corporation

    发明人： Debendra Das Sharma ,  Swadesh Choudhary ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

    IPC分类号： G06F13/42

    摘要： A port is to couple to another die over a die-to-die (D2D) link and includes physical layer (PHY) circuitry including a first number of sideband lanes to carry data for use in training and management of the D2D link, and a second number of mainband lanes to implement a main data path of the D2D link. The mainband lanes include a forwarded clock lane, a valid lane, and a plurality of data lanes. A logical PHY coordinates functions of the sideband lanes and the mainband lanes.

    POWER-FORWARDING BRIDGE FOR INTER-CHIP DATA SIGNAL TRANSFER
    2.
    发明申请
    POWER-FORWARDING BRIDGE FOR INTER-CHIP DATA SIGNAL TRANSFER 有权

    公开(公告)号：US20220199537A1

    公开(公告)日：2022-06-23

    申请号：US17127304

    申请日：2020-12-18

    申请人： Intel Corporation

    发明人： Zhiguo Qian ,  Gerald Pasdast ,  Peipei Wang ,  Daniel Krueger ,  Edward Burton

    IPC分类号： H01L23/538 ,  H01L23/50 ,  H01L25/065 ,  H01L21/50

    摘要： An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.

    COMPOSITE INTERPOSER STRUCTURE AND METHOD OF PROVIDING SAME
    3.
    发明申请
    COMPOSITE INTERPOSER STRUCTURE AND METHOD OF PROVIDING SAME 有权

    公开(公告)号：US20210159179A1

    公开(公告)日：2021-05-27

    申请号：US16698557

    申请日：2019-11-27

    申请人： Intel Corporation

    发明人： Adel Elsherbini ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast

    IPC分类号： H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

    摘要： Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

    Composite interposer structure and method of providing same
    6.
    发明授权
    Composite interposer structure and method of providing same 有权

    公开(公告)号：US11652059B2

    公开(公告)日：2023-05-16

    申请号：US17536804

    申请日：2021-11-29

    申请人： INTEL CORPORATION

    发明人： Adel Elsherbini ,  Shawna Lift ,  Johanna Swan ,  Gerald Pasdast

    IPC分类号： H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

    CPC分类号： H01L23/5385 ,  H01L21/3043 ,  H01L21/4846 ,  H01L24/20

    摘要： Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

    COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT
    9.
    发明申请
    COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT 有权

    公开(公告)号：US20220318111A1

    公开(公告)日：2022-10-06

    申请号：US17844348

    申请日：2022-06-20

    申请人： Intel Corporation

    发明人： Swadesh Choudhary ,  Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Zuoguo Wu ,  Gerald Pasdast

    IPC分类号： G06F11/263 ,  G06F13/42

    摘要： In one embodiment, an apparatus comprises a first die that includes: a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to receive message information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter, the physical layer circuity comprising a plurality of second registers, where the physical layer circuitry is to receive and output the message information to a second die via an interconnect having a mainband and a sideband. During a test of the apparatus, the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers. Other embodiments are described and claimed.

    Composite interposer structure and method of providing same
    10.
    发明授权
    Composite interposer structure and method of providing same 有权

    公开(公告)号：US11270947B2

    公开(公告)日：2022-03-08

    申请号：US16698557

    申请日：2019-11-27

    申请人： Intel Corporation

    发明人： Adel Elsherbini ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast

    IPC分类号： H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

    摘要： Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.