公开(公告)号：US20190318204A1

公开(公告)日：2019-10-17

申请号：US16452040

申请日：2019-06-25

申请人： Intel Corporation

发明人： Yatish Mishra ,  Cesar Martinez-Spessot ,  Alexander Heinecke ,  Justin Gottschlich

IPC分类号： G06K9/62 ,  G06N20/00 ,  G06Q10/06

摘要： Methods and apparatus to manage tickets are disclosed. A disclosed example apparatus includes a ticket analyzer to read data corresponding to open tickets, a machine learning model processor to apply a machine learning model to files associated with previous tickets based on the read data to determine probabilities of relationships between the files and the open tickets, a grouping analyzer to identify at least one of a grouping or a dependency between the open tickets based on the determined probabilities, and a ticket data writer to store data associated with the at least one of the grouping or the dependency.

公开(公告)号：US20190317734A1

公开(公告)日：2019-10-17

申请号：US16456984

申请日：2019-06-28

申请人： Intel Corporation

发明人： Li Chen ,  Justin Gottschlich ,  Alexander Heinecke ,  Zheng Zhang ,  Shengtian Zhou

IPC分类号： G06F8/33 ,  G06N3/08

摘要： Methods, apparatus, systems and articles of manufacture are disclosed to improve code characteristics. An example apparatus includes a weight manager to apply a first weight value to a first objective function, a state identifier to identify a first state corresponding to candidate code, and an action identifier to identify candidate actions corresponding to the identified first state. The example apparatus also includes a reward calculator to determine reward values corresponding to respective ones of (a) the identified first state, (b) one of the candidate actions and (c) the first weight value, and a quality function definer to determine a relative highest state and action pair reward value based on respective ones of the reward values

公开(公告)号：US20190225213A1

公开(公告)日：2019-07-25

申请号：US16370855

申请日：2019-03-29

申请人： Intel Corporation

发明人： Alexander Heinecke ,  Sara Baghsorkhi ,  Justin Gottschlich ,  Mohammad Mejbah Ul Alam ,  Shengtian Zhou ,  Jeffrey Ota

IPC分类号： B60W30/09 ,  B60W30/095 ,  B60W50/00 ,  B60W10/18 ,  B60W10/20 ,  B60T8/1755 ,  G06N20/00

摘要： Methods, apparatus, systems, and articles of manufacture are disclosed herein that mitigate hard-braking events. An example apparatus includes a world generator to generate a deep learning model to identify and categorize an object in a proximity of a vehicle, a data analyzer to determine a danger level associated with the object, the danger level indicative of a likelihood of a collision between the vehicle and the object, a vehicle response determiner to determine, based on the danger level, a response of the vehicle to avoid a collision with the object, and an instruction generator to transmit instructions to a steering system or a braking system of the vehicle based on the determined vehicle response.

公开(公告)号：US20240045688A1

公开(公告)日：2024-02-08

申请号：US17958369

申请日：2022-10-01

申请人： Intel Corporation

发明人： Alexander Heinecke ,  Menachem Adelman ,  Evangelos Georganas ,  Amit Gradstein ,  Christopher Hughes ,  Naveen Mellempudi ,  Simon Rubanovich ,  Uri Sherman ,  Zeev Sperber

IPC分类号： G06F9/30 ,  G06F7/487

CPC分类号： G06F9/3016 ,  G06F7/4876 ,  G06F9/3001

摘要： Techniques for performing FP8 FMA in response to an instruction are described. In some examples, an instruction has fields for an opcode, an identification of location of a packed data source/destination operand (a first source), an identification of a location of a second packed data source operand, an identification of a location of a third packed data source operand, and an identification of location of a packed data source/destination operand, wherein the opcode is to indicate operand ordering and that execution circuitry is to, per data element position, perform a FP8 value fused multiply-accumulate operation using the first, second, and third source operands and store a result in a corresponding data element position of the source/destination operand, wherein the FP8 value has an 8-bit floating point format that comprises one bit for a sign, at least 4 bits for an exponent, and at least two bits for a fraction.

公开(公告)号：US20240045686A1

公开(公告)日：2024-02-08

申请号：US17958382

申请日：2022-10-01

申请人： Intel Corporation

发明人： Alexander Heinecke ,  Menachem Adelman ,  Evangelos Georganas ,  Amit Gradstein ,  Christopher Hughes ,  Naveen Mellempudi ,  Simon Rubanovich ,  Uri Sherman ,  Zeev Sperber

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30025

摘要： Techniques for converting FP8 data elements to FP16 or FP32 data elements using a single instruction are described. An example apparatus includes decoder circuitry to decode a single instruction, the single instruction to indicate that execution circuitry is to convert packed FP8 data from the identified source to packed half-precision floating-point data or single-precision floating point data and store the packed half-precision floating-point data or single-precision floating point data into corresponding data element positions of the identified destination operand.

公开(公告)号：US20240045685A1

公开(公告)日：2024-02-08

申请号：US17958381

申请日：2022-10-01

申请人： Intel Corporation

发明人： Menachem Adelman ,  Amit Gradstein ,  Alexander Heinecke ,  Christopher Hughes ,  Naveen Mellempudi ,  Shahar Mizrahi ,  Dana Rip ,  Simon Rubanovich ,  Uri Sherman ,  Guy Boudoukh ,  Evangelos Georganas ,  Nilesh Jain ,  Barukh Ziv

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30025 ,  G06F9/3001

摘要： Systems, methods, and apparatuses relating sparsity based FMA. In some examples, an instance of a single FMA instruction has one or more fields for an opcode, one or more fields to identify a source/destination matrix operand, one or more fields to identify a first plurality of source matrix operands, one or more fields to identify a second plurality of matrix operands, wherein the opcode is to indicate that execution circuitry is to select a proper subset of FP8 data elements from the first plurality of source matrix operands based on sparsity controls from a first matrix operand of the second plurality of matrix operands and perform a FMA.

公开(公告)号：US20240045681A1

公开(公告)日：2024-02-08

申请号：US17958367

申请日：2022-10-01

申请人： Intel Corporation

发明人： Alexander Heinecke ,  Menachem Adelman ,  Evangelos Georganas ,  Amit Gradstein ,  Christopher Hughes ,  Naveen Mellempudi ,  Simon Rubanovich ,  Uri Sherman ,  Zeev Sperber

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30036 ,  G06F9/30094

摘要： Techniques for comparing FP8 data elements are described. An exemplary FP8 comparison instruction includes fields for an opcode, an identification of a location of a first packed data source operand, and an identification of a location of a second packed data source operand, wherein the opcode is to indicate that execution circuitry is to perform, for a particular data element position of the packed data source operands, a comparison of a data element at that position, and update a flags register based on the comparison.

公开(公告)号：US20230418750A1

公开(公告)日：2023-12-28

申请号：US17852189

申请日：2022-06-28

申请人： Intel Corporation

发明人： Yedidya Hilewitz ,  Monam Agarwal ,  Yen-Cheng Liu ,  Alexander Heinecke

IPC分类号： G06F12/0815 ,  G06F12/0811 ,  G06F12/084

CPC分类号： G06F12/0815 ,  G06F12/0811 ,  G06F12/084

摘要： Techniques for hierarchical core valid tracking are described. An example apparatus comprises a cache to store information accessible by two or more cores, and circuitry coupled to the cache to maintain coherence of the information stored in the cache and to hierarchically track respective associations of the information stored in the cache with the two or more cores, where a lowest hierarchical level of the hierarchically tracked associations is to indicate a logical core identifier of a particular core of the two or more cores. Other examples are disclosed and claimed.

公开(公告)号：US20230385059A1

公开(公告)日：2023-11-30

申请号：US18449651

申请日：2023-08-14

申请人： Intel Corporation

发明人： Raanan Sade ,  Simon Rubanovich ,  Amit Gradstein ,  Zeev Sperber ,  Alexander Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Bret Toll ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3001 ,  G06F9/30145 ,  G06F9/3005 ,  G06F9/30036 ,  G06F9/383 ,  G06F9/3016 ,  G06F9/30109 ,  G06F9/30123 ,  G06F9/30076 ,  G06F9/3824 ,  G06F9/30043

摘要： Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (M,N) of the identified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the identified first source matrix by a corresponding nibble of a doubleword element (K,N) of the identified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element (M,N).

公开(公告)号：US20230256961A1

公开(公告)日：2023-08-17

申请号：US18104923

申请日：2023-02-02

申请人： Intel Corporation

发明人： Alexander Heinecke ,  Sara Baghsorkhi ,  Justin Gottschlich ,  Mohammad Mejbah Ul Alam ,  Shengtian Zhou ,  Jeffrey Ota

IPC分类号： B60W30/09 ,  B60W30/095 ,  B60W50/00 ,  G06N20/00 ,  B60W10/20 ,  B60T8/1755 ,  B60W10/18

CPC分类号： B60W30/09 ,  B60W30/0956 ,  B60W50/0098 ,  G06N20/00 ,  B60W10/20 ,  B60T8/17555 ,  B60T8/17558 ,  B60W10/18 ,  B60T2260/02 ,  B60T2270/86 ,  B60T2210/32

摘要： Methods, apparatus, systems, and articles of manufacture are disclosed herein that mitigate hard-braking events. An example apparatus at least one memory; instructions; and processor circuitry to execute the instructions to: determine a danger level associated with an object, the danger level indicative of a first measure of damage corresponding to a trajectory of the object compared to a trajectory of a vehicle; determine, based on the first danger level, a danger measure based on at least one of a position of the object, a velocity of the object, an acceleration of the object, a direction of travel of the object, a weight or mass of the object; and generate instructions to transmit to a steering system or a braking system of the vehicle based on the determination.