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    Estimating multi-person poses using greedy part assignment
    64.
    发明授权
    Estimating multi-person poses using greedy part assignment 有权

    公开(公告)号：US10430966B2

    公开(公告)日：2019-10-01

    申请号：US15480204

    申请日：2017-04-05

    Applicant: INTEL CORPORATION

    Inventor： Srenivas Varadarajan ,  Omesh Tickoo ,  Parual Datta

    IPC: G06T7/73 ,  G06K9/00 ,  G06K9/62

    Abstract: An example apparatus for estimating poses includes a person estimator to estimate a number of people based on a significant head count of received refined part detections. The apparatus includes a detection clusterer to cluster the refined part detections based on the estimated number of people to generate clustered part detections. The apparatus includes a candidate selector to select candidate person clusters for each clustered part detection based on proximity to the clustered part detection. The apparatus includes a sequential assigner to calculate a cluster affinity score for each combination of candidate person cluster and clustered part detection, and greedily sequentially assign each clustered part detection to a candidate person cluster based on the cluster affinity score to generate person clusters. The apparatus includes a pose generator to generate a pose for each person cluster.

    Real Time Video Summarization
    66.
    发明申请
    Real Time Video Summarization 审中-公开

    公开(公告)号：US20170330040A1

    公开(公告)日：2017-11-16

    申请号：US15662815

    申请日：2017-07-28

    Applicant: Intel Corporation

    Inventor： Shayok Chakraborty ,  Omesh Tickoo ,  Ravishankar Iyer

    IPC: G06K9/00 ,  G11B27/30 ,  G11B20/10 ,  G06K9/62

    Abstract: System, apparatus, method, and computer readable media for on-the-fly captured video summarization. A video stream is incrementally summarized in concurrence with generation of the stream by a camera module. Saliency of the video stream summary is maintained as the stream evolves by updating the summary to include only the most significant frames. In one exemplary embodiment, saliency is determined by optimizing an objective function including terms that are indicative of both the diversity of a selection, and how representative the selection is to the processed portion of the video data corpus. A device platform including a CM and comporting with the exemplary architecture may provide video camera functionality at ultra-low power, and/or with ultra-low storage resources, and/or with ultra-low communication channel bandwidth.

    Composable thin computing device
    67.
    发明授权
    Composable thin computing device 有权
    可组合瘦计算设备

    公开(公告)号：US09588581B2

    公开(公告)日：2017-03-07

    申请号：US14022868

    申请日：2013-09-10

    Applicant: Intel Corporation

    Inventor： Anthony G. Lamarca ,  Omesh Tickoo ,  Maynard C. Falconer ,  Shilpa Talwar ,  Wen-Ling M. Huang

    IPC: G06F1/16 ,  G06F3/01 ,  H04M1/02

    CPC classification number: G06F3/011 ,  G06F1/163 ,  G06F1/1635 ,  G06F1/1698 ,  H04M1/0256

    Abstract: This disclosure is directed to a composable thin computing device. An example device may comprise at least a device interface module, a communication module, a processing module, a memory module, a composable computing module and a power module. The device interface module may couple the device to an operational environment via at least one of a physical connector or a wireless connection. The communication module may at least one of transmit or receive data via the device interface module. The processing module may process the data. The memory module may store at least a portion of the data. The composable computing module may cause at least one of the above modules to perform certain functionality related to the operational environment. The power module may power at least one of the above modules.

    Abstract translation: 本公开涉及可组合的薄计算设备。 示例性设备可以包括至少设备接口模块，通信模块，处理模块，存储器模块，可组合计算模块和功率模块。 设备接口模块可以经由物理连接器或无线连接中的至少一个将设备耦合到操作环境。 通信模块可以经由设备接口模块发送或接收数据中的至少一个。 处理模块可以处理数据。 存储器模块可以存储数据的至少一部分。 可组合计算模块可以使至少一个上述模块执行与操作环境相关的某些功能。 电源模块可以为上述模块中的至少一个供电。

    AUGMENTATION OF STOP-MOTION CONTENT
    68.
    发明申请
    AUGMENTATION OF STOP-MOTION CONTENT 审中-公开
    停止运动内容的补充

    公开(公告)号：US20160171739A1

    公开(公告)日：2016-06-16

    申请号：US14567117

    申请日：2014-12-11

    Applicant: Intel Corporation

    Inventor： Glen J. Anderson ,  Wendy March ,  Kathy Yuen ,  Ravishankar Iyer ,  Omesh Tickoo ,  Jeffrey M. Ota ,  Michael E. Kounavis

    IPC: G06T13/80 ,  G06T19/00

    CPC classification number: G06T13/80 ,  G06T11/60 ,  G06T19/006 ,  G11B27/036 ,  G11B27/28 ,  H04S7/303 ,  H04S2400/11 ,  H04S2400/15

    Abstract: Apparatuses, methods and storage media for providing augmented reality (AR) effects in stop-motion content are described. In one instance, an apparatus may include a processor, a content module to be operated by the processor to obtain a plurality of frames having stop-motion content, some of which may include an indication of an augmented reality effect, and an augmentation module to be operated by the processor to detect the indication of the augmented reality effect and add the augmented reality effect corresponding to the indication to some of the plurality of frames. Other embodiments may be described and claimed.

    Abstract translation: 描述了用于在停止运动内容中提供增强现实（AR）效应的装置，方法和存储介质。 在一种情况下，装置可以包括处理器，要由处理器操作的内容模块以获得具有停止运动内容的多个帧，其中一些帧可以包括增强现实效果的指示，以及增强模块， 由处理器操作以检测增强现实效果的指示，并将对应于指示的增强现实效果添加到多个帧中的一些帧。 可以描述和要求保护其他实施例。

    Probabilistic in-memory computing
    70.
    发明授权
    Probabilistic in-memory computing 有权

    公开(公告)号：US11900979B2

    公开(公告)日：2024-02-13

    申请号：US17508818

    申请日：2021-10-22

    Applicant: INTEL CORPORATION

    Inventor： Hai Li ,  Dmitri E. Nikonov ,  Punyashloka Debashis ,  Ian A. Young ,  Mahesh Subedar ,  Omesh Tickoo

    IPC: G11C11/16 ,  G06F7/544 ,  G11C11/54 ,  G06N3/045 ,  G06N3/047

    CPC classification number: G11C11/1673 ,  G06F7/5443 ,  G06N3/045 ,  G06N3/047 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/54

    Abstract: Embodiments of the present disclosure are directed toward probabilistic in-memory computing configurations and arrangements, and configurations of probabilistic bit devices (p-bits) for probabilistic in-memory computing. concept with emerging. A probabilistic in-memory computing device includes an array of p-bits, where each p-bit is disposed at or near horizontal and vertical wires. Each p-bit is a time-varying resistor that has a time-varying resistance, which follows a desired probability distribution. The time-varying resistance of each p-bit represents a weight in a weight matrix of a stochastic neural network. During operation, an input voltage is applied to the horizontal wires to control the current through each p-bit. The currents are accumulated in the vertical wires thereby performing respective multiply-and-accumulative (MAC) operations. Other embodiments may be described and/or claimed.

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