公开(公告)号：US20240429301A1

公开(公告)日：2024-12-26

申请号：US18341467

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Dmitri Evgenievich Nikonov ,  Kevin P. O'Brien ,  John J. Plombon ,  Tristan A. Tronic ,  Ian Alexander Young ,  Matthew V. Metz ,  Marko Radosavljevic ,  Carly Rogan ,  Brandon Holybee ,  Raseong Kim ,  Punyashloka Debashis ,  Dominique A. Adams ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Gauri Auluck ,  Scott B. Clendenning ,  Pratyush P. Buragohain

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: A transistor device may be formed with a doped perovskite material as a channel region. The doped perovskite material may be formed via an epitaxial growth process from a seed layer, and the channel regions of the transistor device may be formed from lateral overgrowth from the epitaxial growth process.

公开(公告)号：US20240105822A1

公开(公告)日：2024-03-28

申请号：US17953648

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Brandon Holybee ,  Carly Rogan ,  Dmitri Evgenievich Nikonov ,  Punyashloka Debashis ,  Rachel A. Steinhardt ,  Tristan A. Tronic ,  Ian Alexander Young ,  Marko Radosavljevic ,  John J. Plombon

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66969

Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.

公开(公告)号：US20230058938A1

公开(公告)日：2023-02-23

申请号：US17409483

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dmitri Evgenievich Nikonov ,  Hai Li ,  Chia-Ching Lin ,  Raseong Kim ,  Tanay A. Gosavi ,  Ashish Verma Penumatcha ,  Uygar E. Avci ,  Marko Radosavljevic ,  Ian Alexander Young

IPC: G11C11/22 ,  H01L27/1159

Abstract: A pbit device, in one embodiment, includes a first field-effect transistor (FET) that includes a source region, a drain region, a source electrode on the source region, a drain electrode on the drain region, a channel region between the source and drain regions, a dielectric layer on a surface over the channel region, an electrode layer above the dielectric layer, and a ferroelectric (FE) material layer between the dielectric layer and the electrode layer. The pbit device also includes a second FET comprising a source electrode, a drain electrode, and a gate electrode. The drain electrode of the second FET is connected to the drain electrode of the first FET.

公开(公告)号：US20250006841A1

公开(公告)日：2025-01-02

申请号：US18345127

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Rachel A. Steinhardt ,  Punyashloka Debashis ,  Kevin P. O'Brien ,  Matthew V. Metz ,  Scott B. Clendenning ,  Brandon Holybee ,  Marko Radosavljevic ,  Ian Alexander Young ,  I-Cheng Tung ,  Sudarat Lee ,  Raseong Kim ,  Pratyush P. Buragohain

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/221 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a transistor includes a gate of strontium ruthenate and a ferroelectric gate dielectric layer of barium titanate. In order to prevent migration of ruthenium from the strontium ruthenate to the barium titanate, a barrier layer is placed between the gate and the ferroelectric gate dielectric layer. The barrier layer may be a metal oxide, such as strontium oxide, barium oxide, zirconium oxide, etc.

公开(公告)号：US20250006839A1

公开(公告)日：2025-01-02

申请号：US18343203

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  Rachel A. Steinhardt ,  Pratyush P. Buragohain ,  John J. Plombon ,  Hai Li ,  Gauri Auluck ,  I-Cheng Tung ,  Tristan A. Tronic ,  Dominique A. Adams ,  Punyashloka Debashis ,  Raseong Kim ,  Carly Rogan ,  Arnab Sen Gupta ,  Brandon Holybee ,  Marko Radosavljevic ,  Uygar E. Avci ,  Ian Alexander Young ,  Matthew V. Metz

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/49 ,  H01L29/66

Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first p-type perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second p-type perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.

公开(公告)号：US20230284538A1

公开(公告)日：2023-09-07

申请号：US17685053

申请日：2022-03-02

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Chia-Ching Lin ,  Hai Li ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L43/06 ,  H01L27/22 ,  H01L43/14 ,  H01F10/32 ,  G11C11/18 ,  G11C11/16 ,  H03K19/18

CPC classification number: H01L43/06 ,  H01L27/228 ,  H01L43/14 ,  H01F10/3286 ,  H01F10/3268 ,  G11C11/18 ,  G11C11/1673 ,  G11C11/1675 ,  H03K19/18 ,  H01L43/10

Abstract: A spin orbit logic device includes: a first electrically conductive layer; a layer including a magnetoelectric material (ME layer) on the first electrically conductive layer; a layer including a ferromagnetic material with in-plane magnetic anisotropy (FM layer) on the ME layer; a second electrically conductive layer on the FM layer; a layer including a dielectric material on the second electrically conductive layer (coupling layer); a layer including a spin orbit coupling material (SOC layer) on the coupling layer; and a layer including a ferromagnetic material with perpendicular magnetic anisotropy (PMA layer) on the SOC layer.

公开(公告)号：US20230070486A1

公开(公告)日：2023-03-09

申请号：US17467124

申请日：2021-09-03

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Hai Li

IPC: G11C11/16 ,  G06F7/58 ,  G06F17/16

Abstract: Technologies for non-uniform random number generation are disclosed. In one embodiment, the distribution of resistance of a magnetic tunnel junction (MTJ) can be controlled by applying a mechanical strain with a piezoelectric layer and by applying a spin torque by a spin-orbit torque layer. The distribution of resistance can be approximately a Gaussian distribution. In another embodiment, an array of N probabilistic bits (p-bits) has a bias and feedback matrix that result in the array of p-bits outputting an N-bit random number with a non-uniform distribution, such as a Gaussian distribution.

公开(公告)号：US20250008852A1

公开(公告)日：2025-01-02

申请号：US18346212

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dominique A. Adams ,  Gauri Auluck ,  Scott B. Clendenning ,  Arnab Sen Gupta ,  Brandon Holybee ,  Raseong Kim ,  Matthew V. Metz ,  Kevin P. O'Brien ,  John J. Plombon ,  Marko Radosavljevic ,  Carly Rogan ,  Hojoon Ryu ,  Rachel A. Steinhardt ,  Tristan A. Tronic ,  I-Cheng Tung ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov

IPC: H10N70/00 ,  H10B63/00 ,  H10B99/00

Abstract: A two-terminal ferroelectric perovskite diode comprises a region of ferroelectric perovskite material positioned adjacent to a region of n-type doped perovskite semiconductor material. Asserting a positive voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a first direction that causes the diode to be placed in a low resistance state due to the formation of an accumulation region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor boundary. Asserting a negative voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a second direction that causes the diode to be placed in a high resistance state due to the formation of a depletion region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor material. These non-volatile low and high resistance states enable the diode to be used as a non-volatile memory element.

公开(公告)号：US20240224814A1

公开(公告)日：2024-07-04

申请号：US18148240

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young ,  Hai Li

IPC: H10N50/85 ,  G11C11/16 ,  H01F10/32 ,  H03K19/18 ,  H10N52/80

CPC classification number: H10N50/85 ,  G11C11/161 ,  H01F10/3286 ,  H03K19/18 ,  H10N52/80

Abstract: Valleytronic magnetoelectric spin-orbit (MESO) logic devices comprise a charge-to-spin conversion input module that comprises a magnetoelectric capacitor. The input module converts a differential input voltage into a magnetization orientation of a ferromagnet possessing in-plane anisotropy (IPA) through exchange coupling between the IPA ferromagnet and the magnetoelectric layer of the capacitor. The magnetization orientation of the IPA ferromagnet can represent the logic state of the valleytronic MESO device. A spin-to-charge conversion output module comprises a ferromagnet possessing perpendicular magnetic anisotropy (PMA) and a 2D valleytronic material. The IMA and PMA ferromagnets are chirally-coupled through Dzaloshinskii-Moriya interaction, which causes the perpendicular magnetic orientation of the PMA ferromagnet to switch with the in-plane magnetization orientation of the IPA ferromagnet. The logic state of the device is read through injection of spin-polarized current from the PMA ferromagnet into the 2D valleytronic layer, which converts the injected spin-polarized current into a differential output current.

公开(公告)号：US20230320230A1

公开(公告)日：2023-10-05

申请号：US17709074

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L43/10 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14 ,  H01L27/22

CPC classification number: H01L43/10 ,  H01L43/04 ,  H01L43/065 ,  H01L43/14 ,  H01L27/228 ,  H03K19/18

Abstract: In one embodiment, an integrated circuit die includes: a first layer comprising a magnetoelectric material; a second layer comprising a monolayer transition metal dichalcogenide (TMD); a magnet between the first layer and the second layer, wherein the magnet has perpendicular magnetic anisotropy; a first conductive trace coupled to the first layer; and a second conductive trace coupled to the magnet.