公开(公告)号：US20250006840A1

公开(公告)日：2025-01-02

申请号：US18344022

申请日：2023-06-29

Applicant: INTEL CORPORATION

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Tristan A. Tronic ,  Ian Alexander Young ,  Matthew V. Metz ,  Marko Radosavljevic ,  Carly Rogan ,  Brandon Holybee ,  Raseong Kim ,  Punyashloka Debashis ,  Dominique A. Adams ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Gauri Auluck ,  Scott B. Clendenning ,  Pratyush P. Buragohain ,  Hai Li

IPC: H01L29/78 ,  H01L29/76 ,  H01L29/786

Abstract: In one embodiment, a negative capacitance transistor device includes a perovskite semiconductor material layer with first and second perovskite conductors on opposite ends of the perovskite semiconductor material layer. The device further includes a dielectric material layer on the perovskite semiconductor material layer between the first and second perovskite conductors, a perovskite ferroelectric material layer on the dielectric material layer, and a third perovskite conductor on the perovskite ferroelectric material layer.

公开(公告)号：US20240206348A1

公开(公告)日：2024-06-20

申请号：US18083493

申请日：2022-12-17

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Hai Li

IPC: H10N52/85 ,  G11C11/16 ,  H03K19/20 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85

CPC classification number: H10N52/85 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H03K19/20 ,  H10B61/22 ,  H10N50/10 ,  H10N50/85

Abstract: In embodiments herein, probabilistic and deterministic logic devices include reduced symmetry materials, such as two-dimensional (2D) transition metal dichalcogenide (TMD) materials (e.g., NbSe2 or MoTe2).

公开(公告)号：US11900979B2

公开(公告)日：2024-02-13

申请号：US17508818

申请日：2021-10-22

Applicant: INTEL CORPORATION

Inventor： Hai Li ,  Dmitri E. Nikonov ,  Punyashloka Debashis ,  Ian A. Young ,  Mahesh Subedar ,  Omesh Tickoo

IPC: G11C11/16 ,  G06F7/544 ,  G11C11/54 ,  G06N3/045 ,  G06N3/047

CPC classification number: G11C11/1673 ,  G06F7/5443 ,  G06N3/045 ,  G06N3/047 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/54

Abstract: Embodiments of the present disclosure are directed toward probabilistic in-memory computing configurations and arrangements, and configurations of probabilistic bit devices (p-bits) for probabilistic in-memory computing. concept with emerging. A probabilistic in-memory computing device includes an array of p-bits, where each p-bit is disposed at or near horizontal and vertical wires. Each p-bit is a time-varying resistor that has a time-varying resistance, which follows a desired probability distribution. The time-varying resistance of each p-bit represents a weight in a weight matrix of a stochastic neural network. During operation, an input voltage is applied to the horizontal wires to control the current through each p-bit. The currents are accumulated in the vertical wires thereby performing respective multiply-and-accumulative (MAC) operations. Other embodiments may be described and/or claimed.

公开(公告)号：US20230284457A1

公开(公告)日：2023-09-07

申请号：US17688495

申请日：2022-03-07

Applicant: Intel Corporation

Inventor： Hai Li ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Punyashloka Debashis ,  Ian Alexander Young ,  Julien Sebot

IPC: H01L27/22 ,  H01L43/04 ,  H01L43/06

CPC classification number: H01L27/22 ,  H01L43/04 ,  H01L43/06

Abstract: In one embodiment, a first integrated circuit component, a second integrated circuit component, and an electrical interconnect coupling the first integrated circuit component and the second integrated circuit component. The interconnect comprises one or more spintronic logic devices.

公开(公告)号：US20230100649A1

公开(公告)日：2023-03-30

申请号：US17485265

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Magnetoelectric magnetic tunnel junction (MEMTJ) logic devices comprise a magnetoelectric switching capacitor coupled to a pair of magnetic tunnel junctions (MTJs) by an insulating layer. The logic state of the MEMTJ is represented by the magnetization orientation of the ferromagnetic layer of the magnetoelectric capacitor and can be switched through the application of an input voltage to the MEMTJ that causes the magnetoelectric switching capacitor to switch states. The magnetization orientation of the magnetoelectric capacitor ferromagnetic layer is read out by the MTJs. The magnetization orientation of a ferromagnetic free layer common to the MTJs is coupled to the ferromagnetic layer of the magnetoelectric capacitor. The potential of the ferromagnetic free layer is based on the power supply voltage applied to the ferromagnetic reference layer of the MTJ having a magnetization orientation parallel to that of the ferromagnetic free layer.

公开(公告)号：US20240114692A1

公开(公告)日：2024-04-04

申请号：US17958395

申请日：2022-10-01

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Uygar E. Avci ,  Vachan Kumar ,  Hai Li ,  Yu-Ching Liao ,  Ian Alexander Young

IPC: H01L27/11502 ,  G11C11/22 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L27/11502 ,  G11C11/221 ,  G11C11/223 ,  H01L27/1087 ,  H01L29/945

Abstract: Inverted pillar capacitors that have a U-shaped insulating layer are oriented with the U-shaped opening of the insulating layer opening toward the surface of the substrate on which the inverted pillar capacitors are formed. The bottom electrodes of adjacent inverted pillar capacitors are isolated from each other by the insulating layers of the adjacent electrodes and the top electrode that fills the volume between the electrodes. By avoiding the need to isolate adjacent bottom electrodes by an isolation dielectric region, inverted pillar capacitors can provide for a greater capacitor density relative to non-inverted pillar capacitors. The insulating layer in inverted pillar capacitors can comprise a ferroelectric material or an antiferroelectric material. The inverted pillar capacitor can be used in memory circuits (e.g., DRAMs) or non-memory applications.

公开(公告)号：US20230200079A1

公开(公告)日：2023-06-22

申请号：US17555207

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Tanay A. Gosavi ,  Uygar E. Avci ,  Sou-Chi Chang ,  Hai Li ,  Dmitri Evgenievich Nikonov ,  Kaan Oguz ,  Ashish Verma Penumatcha ,  John J. Plombon ,  Ian Alexander Young

IPC: H01L27/11514 ,  H01L49/02 ,  H01L29/51

CPC classification number: H01L27/11514 ,  H01L28/65 ,  H01L29/516

Abstract: A first type of ferroelectric capacitor comprises electrodes and an insulating layer comprising ferroelectric oxides. In some embodiments, the electrodes and the insulating layer comprise perovskite ferroelectric oxides. A second type of ferroelectric capacitor comprises a ferroelectric insulating layer comprising certain monochalcogenides. Both types of ferroelectric capacitors can have a coercive voltage that is less than one volt. Such capacitors are attractive for use in low-voltage non-volatile embedded memories for next-generation semiconductor manufacturing technologies.

公开(公告)号：US20230058938A1

公开(公告)日：2023-02-23

申请号：US17409483

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dmitri Evgenievich Nikonov ,  Hai Li ,  Chia-Ching Lin ,  Raseong Kim ,  Tanay A. Gosavi ,  Ashish Verma Penumatcha ,  Uygar E. Avci ,  Marko Radosavljevic ,  Ian Alexander Young

IPC: G11C11/22 ,  H01L27/1159

Abstract: A pbit device, in one embodiment, includes a first field-effect transistor (FET) that includes a source region, a drain region, a source electrode on the source region, a drain electrode on the drain region, a channel region between the source and drain regions, a dielectric layer on a surface over the channel region, an electrode layer above the dielectric layer, and a ferroelectric (FE) material layer between the dielectric layer and the electrode layer. The pbit device also includes a second FET comprising a source electrode, a drain electrode, and a gate electrode. The drain electrode of the second FET is connected to the drain electrode of the first FET.

公开(公告)号：US20200372333A1

公开(公告)日：2020-11-26

申请号：US16989371

申请日：2020-08-10

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Hai Li ,  Ian A. Young

IPC: G06N3/063 ,  H03K3/03

Abstract: Disclosed herein are staged oscillators for neural computing, as well as related methods and assemblies. In some embodiments, neural computing circuitry may include a first oscillator set, a second oscillator set, and an averaging structure coupled between the first oscillator set and the second oscillator set.

公开(公告)号：US20240147867A1

公开(公告)日：2024-05-02

申请号：US17978145

申请日：2022-10-31

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dominique A. Adams ,  Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Kaan Oguz ,  John J. Plombon ,  Ian Alexander Young

IPC: H10N50/10 ,  G11C11/16 ,  H01L23/522 ,  H01L23/528 ,  H10B61/00 ,  H10N50/85

CPC classification number: H10N50/10 ,  G11C11/161 ,  H01L23/5226 ,  H01L23/5283 ,  H10B61/22 ,  H10N50/85

Abstract: Magnetoelectric magnetic tunnel junction (MEMTJ) logic devices comprise a magnetoelectric switching capacitor coupled to a pair of magnetic tunnel junctions (MTJs) by a conductive layer. The logic state of the MEMTJ is represented by the magnetization orientation of the ferromagnetic layer of the magnetoelectric capacitor, which can be switched through the application of an appropriate input voltage to the MEMTJ. The magnetization orientation of the magnetoelectric capacitor ferromagnetic layer is read out by the MTJs. The conductive layer is positioned between the capacitor and the MTJs. The MTJ ferromagnetic free layers are exchange coupled to the ferromagnetic layer of the magnetoelectric capacitor. The potential of an MTJ free layer is based on a supply voltage applied to the reference layer of the MTJ. The MTJ reference layers have a magnetization orientation that is parallel or antiparallel to the magnetization orientations of the ferromagnetic layer of the magnetoelectric capacitor.