公开(公告)号：US12219881B2

公开(公告)日：2025-02-04

申请号：US17485453

申请日：2021-09-26

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

Abstract: A semiconductor device includes a dual layer top contact upon a MTJ stack. The dual layer top contact includes lower contact and upper contact. The lower contact may be wider and/or shallower relative to the upper contact. This wide and/or shallow geometry of the lower contact may decrease the propensity for over etching, during the formation of the upper contact, opening downward into the MTJ stack and may therefore prevent undesired shorting of the MTJ stack. Further, the lower contact may further protect the MTJ stack even when the upper contact is misaligned to the MTJ stack.

公开(公告)号：US12120963B2

公开(公告)日：2024-10-15

申请号：US17484934

申请日：2021-09-24

Applicant: International Business Machines Corporation

Inventor： Lili Cheng ,  Ashim Dutta ,  Chih-Chao Yang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10N50/01 ,  H10B61/22

Abstract: A semiconductor structure comprises a bottom electrode contact, and a memory device comprising a bottom electrode disposed on the bottom electrode contact, at least one memory element layer disposed on the bottom electrode, and a top electrode disposed on the at least one memory element layer. A bit line contact is disposed on the top electrode and extends around sides of the memory device and of the bottom electrode contact. An encapsulation layer is disposed between the bit line contact and the sides of the memory device and of the bottom electrode contact.

公开(公告)号：US12058942B2

公开(公告)日：2024-08-06

申请号：US17513108

申请日：2021-10-28

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a magnetoresistive random access memory (MRAM) cell with a memory array landing pad contacting a first bottom metal level contact and an MRAM pillar electrically connected to the memory array landing pad. The semiconductor structure may also include a logic interconnect contacting a second bottom metal level contact and a dielectric cap above the MRAM cell and the logic interconnect. The MRAM cell and logic interconnect may be electrically connected to a top metal level through the dielectric cap.

公开(公告)号：US11876047B2

公开(公告)日：2024-01-16

申请号：US17447586

申请日：2021-09-14

Applicant: International Business Machines Corporation

Inventor： Saumya Sharma ,  Ashim Dutta ,  Tianji Zhou ,  Chih-Chao Yang

IPC: H01L21/00 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76843 ,  H01L23/5226 ,  H10B61/00 ,  H10B63/00

Abstract: A semiconductor component includes an insulative layer having a lowermost surface arranged on top of a bottom dielectric material. The semiconductor component further includes a first interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the first interconnect structure is arranged at a first height relative to the lowermost surface of the insulative layer. The semiconductor component further includes a pillar connected to the first interconnect structure and extending through the insulative layer. The semiconductor component further includes a second interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the second interconnect structure is arranged at a second height relative to the lowermost surface of the insulative layer. The second height is different than the first height.

公开(公告)号：US11856878B2

公开(公告)日：2023-12-26

申请号：US17453841

申请日：2021-11-06

Applicant: International Business Machines Corporation

Inventor： Dexin Kong ,  Ekmini Anuja De Silva ,  Ashim Dutta ,  Daniel Schmidt

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/841 ,  H10B63/80 ,  H10N70/063 ,  H10N70/24 ,  H10N70/826

Abstract: A high-density resistive random-access memory array with self-aligned bottom electrode contact includes a plurality of electrically conductive structures embedded in an interconnect dielectric material layer, a bottom electrode selectively grown over, and electrically connected to, each of the electrically conductive structures with the bottom electrode above an electrically conductive structure being separated from the bottom electrode above another electrically conductive structure by a first dielectric filling layer, the bottom electrode having a semi-circular shape. The array further includes a resistive random-access memory pillar disposed above the bottom electrode.

公开(公告)号：US20230361158A1

公开(公告)日：2023-11-09

申请号：US17662439

申请日：2022-05-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： HUIMEI ZHOU ,  Baozhen Li ,  Chih-Chao Yang ,  Ashim Dutta

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/532 ,  H01C17/06

CPC classification number: H01L28/24 ,  H01L23/5228 ,  H01L23/5226 ,  H01L23/53295 ,  H01C17/06

Abstract: Embodiments of present invention provide a resistor structure. The resistor structure includes a first layer of electrically insulating material; and a second layer of resistive material directly adjacent to the first layer, wherein thermal conductivity of the first layer is equal to or larger than 100 W/m/K. In one embodiment, the first layer of electrically insulating material has a band gap equal to or larger than 4 eV and is selected from a group consisting of aluminum-nitride (AlN), boron-nitride (BN), and diamond (C).

公开(公告)号：US11812668B2

公开(公告)日：2023-11-07

申请号：US17552027

申请日：2021-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael Rizzolo ,  Theodorus E. Standaert ,  Ashim Dutta ,  Dominik Metzler

IPC: H10N50/80 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/85 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/85 ,  H10N70/026 ,  H10N70/063 ,  H10N70/231 ,  H10N70/826

Abstract: A method for fabricating a semiconductor device includes forming a conductive shell layer along a memory stack and a patterned hardmask disposed on the memory stack, and etching the patterned hardmask, the conductive shell layer and the memory stack to form a structure including a central core surrounded by a conductive outer shell disposed on a patterned memory stack.

公开(公告)号：US20230136650A1

公开(公告)日：2023-05-04

申请号：US17513108

申请日：2021-10-28

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a magnetoresistive random access memory (MRAM) cell with a memory array landing pad contacting a first bottom metal level contact and an MRAM pillar electrically connected to the memory array landing pad. The semiconductor structure may also include a logic interconnect contacting a second bottom metal level contact and a dielectric cap above the MRAM cell and the logic interconnect. The MRAM cell and logic interconnect may be electrically connected to a top metal level through the dielectric cap.

公开(公告)号：US20230098576A1

公开(公告)日：2023-03-30

申请号：US17485453

申请日：2021-09-26

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02

Abstract: A semiconductor device includes a dual layer top contact upon a MTJ stack. The dual layer top contact includes lower contact and upper contact. The lower contact may be wider and/or shallower relative to the upper contact. This wide and/or shallow geometry of the lower contact may decrease the propensity for over etching, during the formation of the upper contact, opening downward into the MTJ stack and may therefore prevent undesired shorting of the MTJ stack. Further, the lower contact may further protect the MTJ stack even when the upper contact is misaligned to the MTJ stack.

公开(公告)号：US11462583B2

公开(公告)日：2022-10-04

申请号：US16672752

申请日：2019-11-04

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Daniel Charles Edelstein ,  John Arnold ,  Theodorus E. Standaert

IPC: H01L27/22 ,  H01L43/12 ,  H01L23/528 ,  H01L43/02

Abstract: A semiconductor device structure includes a metallization stack that has one or more patterned metal layers in a logic area and a memory area. At least one memory device is disposed above the metallization stack. A first level logic metal layer is coupled to a patterned metal layer of the one or more patterned metal layers in the logic area. A first level memory metal layer is formed above the first level logic metal layer and is coupled to a top electrode of the memory device stack. A distance between the one or more patterned metal layers in the logic area and the first level logic metal layer is smaller than the distance between the one or more patterned metal layers in the memory area and the first level memory metal layer.