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    IMPLEMENTING SIMULTANEOUS READ AND WRITE OPERATIONS UTILIZING DUAL PORT DRAM
    62.
    发明申请
    IMPLEMENTING SIMULTANEOUS READ AND WRITE OPERATIONS UTILIZING DUAL PORT DRAM 有权
    实现同时使用双端口DRAM的读取和写入操作

    公开(公告)号：US20150213854A1

    公开(公告)日：2015-07-30

    申请号：US14310717

    申请日：2014-06-20

    Applicant: International Business Machines Corporation

    Inventor： Edgar R. Cordero ,  Carlos A. Fernandez ,  Joab D. Henderson ,  Jeffrey A. Sabrowski ,  Anuwat Saetow ,  Saravanan Sethuraman

    IPC: G11C7/10

    CPC classification number: G11C7/1075 ,  G06F11/1048 ,  G11C7/1045 ,  G11C8/16 ,  G11C2029/0411 ,  G11C2207/2209

    Abstract: A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.

    Abstract translation: 提供了一种方法，系统和存储器控制器，用于在利用双端口动态随机存取存储器（DRAM）配置的存储器子系统中实现同时的读和写操作。 DRAM包括第一分区和第二分区。 存储器控制器确定存储器需求是否高于或低于使用阈值。 如果存储器要求低于使用阈值，则存储器被划分为读缓冲器和写缓冲器，其中写入缓冲器的写入和来自读缓冲器的读取，数据从写缓冲器传送到读缓冲器，通过 纠错码（ECC）引擎。 如果内存要求高于使用阈值，则整个内存将用于读取和写入。

    CHARACTERIZING TSV STRUCTURES IN A SEMICONDUCTOR CHIP STACK
    63.
    发明申请
    CHARACTERIZING TSV STRUCTURES IN A SEMICONDUCTOR CHIP STACK 有权
    在半导体芯片堆栈中表征TSV结构

    公开(公告)号：US20140351783A1

    公开(公告)日：2014-11-27

    申请号：US13901332

    申请日：2013-05-23

    Applicant: International Business Machines Corporation

    Inventor： Anand Haridass ,  Subramanian S. Iyer ,  Saravanan Sethuraman ,  Ming Yin

    IPC: G06F17/50

    CPC classification number: G06F17/5059 ,  G01R31/31725 ,  G01R31/318513 ,  G06F17/5031 ,  G06F17/5081

    Abstract: A first signal is transmitted through a first path. A computing device determines a signal propagation time of the first signal. The computing device transmits a second signal through a second path, wherein the second path includes the second signal traversing across at least one interconnecting structure. The computing device determines a signal propagation time of the second signal. The computing device determines a propagation time difference between the signal propagation time of the first signal and the signal propagation time of the second signal. The computing device adjusts a clock based on the determined propagation time difference.

    Abstract translation: 第一信号通过第一路径发送。 计算装置确定第一信号的信号传播时间。 计算设备通过第二路径发送第二信号，其中第二路径包括穿过至少一个互连结构的第二信号。 计算装置确定第二信号的信号传播时间。 计算装置确定第一信号的信号传播时间与第二信号的信号传播时间之间的传播时间差。 计算装置根据确定的传播时间差来调整时钟。

    SELF MONITORING AND SELF REPAIRING ECC
    64.
    发明申请
    SELF MONITORING AND SELF REPAIRING ECC 有权
    自我监测和自我修复ECC

    公开(公告)号：US20140250340A1

    公开(公告)日：2014-09-04

    申请号：US13781807

    申请日：2013-03-01

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Edgar R. Cordero ,  Timothy J. Dell ,  Joab D. Henderson ,  Jeffrey A. Sabrowski ,  Anuwat Saetow ,  Saravanan Sethuraman

    IPC: G06F11/28

    CPC classification number: G06F11/10 ,  G06F11/1048 ,  G06F11/2017 ,  G06F11/28 ,  H03M13/29

    Abstract: Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment detects that a specified number of correctable errors is exceeded. In another step, an exemplary embodiment detects the occurrence of an uncorrectable error. In another step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.

    Abstract translation: 本发明的示例性实施例公开了一种用于监视第一纠错码（ECC）设备的方法和系统，用于如果第一ECC设备开始失败或失败，则用第二ECC设备故障并替换第一ECC设备。 在一个步骤中，示例性实施例检测到超过了指定数量的可校正错误。 在另一步骤中，示例性实施例检测出不可校正的错误。 在另一步骤中，如果超过指定数量的可校正错误或者发生不可校正的错误，则示例性实施例对ECC设备执行环回测试。 在另一步骤中，示例性实施例用通过环回测试的ECC设备替代了对环回测试失败的ECC设备。

    STACKED CHIP MODULE WITH INTEGRATED CIRCUIT CHIPS HAVING INTEGRATABLE AND RECONFIGURABLE BUILT-IN SELF-MAINTENANCE BLOCKS
    65.
    发明申请
    STACKED CHIP MODULE WITH INTEGRATED CIRCUIT CHIPS HAVING INTEGRATABLE AND RECONFIGURABLE BUILT-IN SELF-MAINTENANCE BLOCKS 有权
    具有集成电路板的堆叠芯片模块，具有可组装和可重构的内置自保护块

    公开(公告)号：US20140110710A1

    公开(公告)日：2014-04-24

    申请号：US13656836

    申请日：2012-10-22

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Kevin W. Gorman ,  Krishnendu Mondal ,  Saravanan Sethuraman

    IPC: H01L23/52 ,  H01L21/66

    CPC classification number: H01L22/34 ,  G01R31/3187 ,  G11C5/04 ,  G11C29/006 ,  G11C29/4401 ,  G11C29/88 ,  H01L23/525 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed is a stacked chip module incorporating a stack of integrated circuit (IC) chips having integratable and automatically reconfigurable built-in self-maintenance blocks (i.e., built-in self-test (BIST) circuits or built-in self-repair (BISR) circuits). Integration of the built-in self-maintenance blocks between the IC chips in the stack allows for servicing (e.g., self-testing or self-repairing) of functional blocks at the module-level. Automatic reconfiguration of the built-in self-maintenance blocks further allows for functional blocks on any of the IC chips in the stack to be serviced at the module-level even when one or more controllers associated with a given built-in self-maintenance block on a given IC chip has been determined to be defective (e.g., during previous wafer-level servicing). Also disclosed is a method of manufacturing and servicing such a stacked chip module.

    Abstract translation: 公开了一种堆叠芯片模块，其包括具有可集成和可自动重新配置的内置自维护块（即，内置自检（BIST）电路或内置自修复（BISR））的集成电路（IC）芯片的堆叠 ）电路）。 在堆叠中的IC芯片之间集成内置的自维护块允许在模块级别对功能块进行维修（例如自检或自修复）。 内置自维护块的自动重新配置进一步允许堆叠中任何IC芯片上的功能块在模块级别被服务，即使当与给定的内置自维护块相关联的一个或多个控制器 在给定的IC芯片上已被确定为有缺陷的（例如，在之前的晶片级维修期间）。 还公开了制造和维护这种堆叠芯片模块的方法。

    Mapping memory allocation requests using various memory attributes
    66.
    发明授权
    Mapping memory allocation requests using various memory attributes 有权

    公开(公告)号：US11307796B2

    公开(公告)日：2022-04-19

    申请号：US16144406

    申请日：2018-09-27

    Applicant: International Business Machines Corporation

    Inventor： Anshuman Khandual ,  Saravanan Sethuraman ,  Venkata K. Tavva ,  Anand Haridass

    IPC: G06F3/06 ,  G06F12/1009 ,  G06F11/07 ,  G06F12/109 ,  G06F16/901

    Abstract: A method stores data that handles page faults in an appropriate memory device based on a standing memory policy. One or more processors receive user requested memory buffer attributes that describe memory buffer attributes needed for various processes. The processor(s) store the user requested memory buffer attributes in an operating system virtual memory representation that describes various types of memories used by the system, create a standing memory policy based on the user requested memory buffer attributes, and store data on an appropriate memory device based on the standing memory policy. The processor(s) receive a page fault, which is based on the data being called by a process but not being currently mapped by a memory management unit (MMU) into a virtual address space of the process. The processor(s) then retrieve and return the data stored on the appropriate memory device in order to address the page fault.

    Block input/output (I/O) accesses in the presence of a storage class memory
    67.
    发明授权
    Block input/output (I/O) accesses in the presence of a storage class memory 有权

    公开(公告)号：US11163475B2

    公开(公告)日：2021-11-02

    申请号：US16431223

    申请日：2019-06-04

    Applicant: International Business Machines Corporation

    Inventor： Vaidyanathan Srinivasan ,  Mehulkumar Patel ,  Saravanan Sethuraman

    IPC: G06F3/06 ,  G06F13/16

    Abstract: Method and apparatus for managing memory includes collocating electronic persistent memory along with a primary memory on a memory module. The electronic persistent memory and the primary memory may communicate via a module local bus comprising a plurality of memory channels. A data migration protocol may be used over a memory channel of the plurality of memory channels to copy data from the electronic persistent memory to the primary memory, and the data may be accessed from the primary memory. The combination of electronic persistent memory and primary memory (e.g. DRAM) in a single memory module with module local bus having a device controller running firmware is one implementation of storage class memory (SCM).

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