公开(公告)号：US07315466B2

公开(公告)日：2008-01-01

申请号：US11191496

申请日：2005-07-28

申请人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

发明人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

摘要翻译： 公开了一种半导体装置及其制造方法。 半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

公开(公告)号：US07276404B2

公开(公告)日：2007-10-02

申请号：US11589618

申请日：2006-10-30

申请人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

发明人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

公开(公告)号：US20070096197A1

公开(公告)日：2007-05-03

申请号：US11642297

申请日：2006-12-20

申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Jong-Hyuk Kim ,  Young-Seop Rah ,  Han-Byung Park

发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Jong-Hyuk Kim ,  Young-Seop Rah ,  Han-Byung Park

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

摘要： A non-volatile memory device includes a semiconductor substrate including a cell array region and a peripheral circuit region. A first cell unit is on the semiconductor substrate in the cell array region, and a cell insulating layer is on the first cell unit. A first active body layer is in the cell insulating layer and over the first cell unit, and a second cell unit is on the first active body layer. The device further includes a peripheral transistor on the semiconductor substrate in the peripheral circuit region. The peripheral transistor has a gate pattern and source/drain regions, and a metal silicide layer is on the gate pattern and/or on the source/drain regions of the peripheral transistor. A peripheral insulating layer is on the metal silicide layer and the peripheral transistor, and an etching protection layer is between the cell insulating layer and the peripheral insulating layer and between the metal silicide layer and the peripheral insulating layer.

摘要翻译： 非易失性存储器件包括包括单元阵列区域和外围电路区域的半导体衬底。 第一单元单元位于单元阵列区域中的半导体基板上，单元绝缘层位于第一单元单元上。 第一有源体层位于单元绝缘层中并在第一单元单元上，第二单元单元位于第一活性体层上。 该器件还包括在外围电路区域中的半导体衬底上的外围晶体管。 外围晶体管具有栅极图案和源极/漏极区域，并且金属硅化物层位于外围晶体管的栅极图案和/或源极/漏极区域上。 外围绝缘层位于金属硅化物层和外围晶体管上，蚀刻保护层位于电池绝缘层和外围绝缘层之间以及金属硅化物层和外围绝缘层之间。

公开(公告)号：US20060270138A1

公开(公告)日：2006-11-30

申请号：US11499946

申请日：2006-08-07

申请人： Young-Chul Jang ,  Sung-Bong Kim ,  Hoon Lim ,  Soon-Moon Jung

发明人： Young-Chul Jang ,  Sung-Bong Kim ,  Hoon Lim ,  Soon-Moon Jung

IPC分类号： H01L21/8238

CPC分类号： H01L29/66621 ,  H01L29/66553

摘要： A transistor includes a substrate and a device isolation layer that is formed on the substrate to define an active region. A gate pattern crosses over the active region. A gate insulation layer is interposed between the gate pattern and the active region. Source and drain regions are formed in the active region adjacent to respective sides of the gate pattern. A channel region is disposed in the active region between the source and drain regions. The channel region includes a recessed portion.

摘要翻译： 晶体管包括衬底和器件隔离层，其形成在衬底上以限定有源区。 栅极模式跨越有源区域。 栅极绝缘层插入在栅极图案和有源区域之间。 源极和漏极区域形成在与栅极图案的相应侧面相邻的有源区域中。 沟道区设置在源区和漏区之间的有源区中。 通道区域包括凹部。

公开(公告)号：US07141851B2

公开(公告)日：2006-11-28

申请号：US10922344

申请日：2004-08-20

申请人： Young-Chul Jang ,  Sung-Bong Kim ,  Hoon Lim ,  Soon-Moon Jung

发明人： Young-Chul Jang ,  Sung-Bong Kim ,  Hoon Lim ,  Soon-Moon Jung

IPC分类号： H01L29/78

CPC分类号： H01L29/66621 ,  H01L29/66553

摘要： A transistor includes a substrate and a device isolation layer that is formed on the substrate to define an active region. A gate pattern crosses over the active region. A gate insulation layer is interposed between the gate pattern and the active region. Source and drain regions are formed in the active region adjacent to respective sides of the gate pattern. A channel region is disposed in the active region between the source and drain regions. The channel region includes a recessed portion.

摘要翻译： 晶体管包括衬底和器件隔离层，其形成在衬底上以限定有源区。 栅极模式跨越有源区域。 栅极绝缘层插入在栅极图案和有源区域之间。 源极和漏极区域形成在与栅极图案的相应侧面相邻的有源区域中。 沟道区设置在源区和漏区之间的有源区中。 通道区域包括凹部。

公开(公告)号：US20060237725A1

公开(公告)日：2006-10-26

申请号：US11364773

申请日：2006-02-28

申请人： Jae-Hun Jeong ,  Soon-Moon Jung ,  Hoon Lim ,  Won-Seok Cho ,  Jin-Ho Kim ,  Chang-Min Hong ,  Jong-Hyuk Kim ,  Kun-Ho Kwak

发明人： Jae-Hun Jeong ,  Soon-Moon Jung ,  Hoon Lim ,  Won-Seok Cho ,  Jin-Ho Kim ,  Chang-Min Hong ,  Jong-Hyuk Kim ,  Kun-Ho Kwak

IPC分类号： H01L29/76 ,  H01L29/00

CPC分类号： H01L27/0688 ,  H01L23/485 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having thin film transistors (TFTs) and methods of fabricating the same are provided. The semiconductor devices include a semiconductor substrate and a lower interlayer insulating layer disposed on the semiconductor substrate. A lower semiconductor body disposed on or in the lower interlayer insulating layer. A lower TFT includes a lower source region and a lower drain region, which are disposed in the lower semiconductor body, and a lower gate electrode, which covers and crosses at least portions of at least two surfaces of the lower semiconductor body disposed between the lower source and drain regions.

摘要翻译： 提供具有薄膜晶体管（TFT）的半导体器件及其制造方法。 半导体器件包括设置在半导体衬底上的半导体衬底和下层间绝缘层。 下部半导体本体设置在下部层间绝缘层上或下部层间绝缘层中。 下部TFT包括设置在下部半导体本体中的下部源极区域和下部漏极区域以及下部栅极电极，该下部栅极电极覆盖并交叉配置在下部半导体器件的下部半导体本体的至少两个表面的至少一部分 源极和漏极区域。

公开(公告)号：US20060049467A1

公开(公告)日：2006-03-09

申请号：US11179236

申请日：2005-07-12

申请人： Hoon Lim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hun Jeong

发明人： Hoon Lim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hun Jeong

IPC分类号： H01L27/01

CPC分类号： H01L29/0847 ,  H01L21/743 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/78612 ,  H01L29/78654

摘要： A metal oxide semiconductor field effect transistor (MOSFET) includes a body pattern of a first conductivity type disposed on an insulating layer. A gate electrode is disposed on the body pattern. A drain region of a second conductivity type is disposed on the insulating layer and having a sidewall in contact with a first sidewall of the body pattern. An impurity-doped region of the first conductivity type is disposed on the insulating layer and having a sidewall in contact with a second sidewall of the body pattern. The MOSFET further includes a source region of the second conductivity type disposed on the impurity-doped region and having a sidewall in contact with the second sidewall of the body pattern, and a contact plug extending through the source region to contact the impurity-doped region.

摘要翻译： 金属氧化物半导体场效应晶体管（MOSFET）包括设置在绝缘层上的第一导电类型的主体图案。 栅电极设置在主体图案上。 第二导电类型的漏极区域设置在绝缘层上并且具有与主体图案的第一侧壁接触的侧壁。 第一导电类型的杂质掺杂区域设置在绝缘层上并且具有与主体图案的第二侧壁接触的侧壁。 MOSFET还包括设置在杂质掺杂区域上并具有与主体图案的第二侧壁接触的侧壁的第二导电类型的源极区域，以及延伸穿过源极区域以接触杂质掺杂区域的接触插塞 。

公开(公告)号：US20050151276A1

公开(公告)日：2005-07-14

申请号：US11032725

申请日：2005-01-11

申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

IPC分类号： H01L21/768 ,  H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/01 ,  H01L27/10 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： A static random-access memory (SRAM) device may include a bulk MOS transistor on a semiconductor substrate having a source/drain region therein, an insulating layer on the bulk MOS transistor, and a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor. The device may further include a multi-layer plug between the bulk MOS transistor and the thin-film transistor. The multi-layer plug may include a semiconductor plug directly on the source/drain region of the bulk MOS transistor and extending through at least a portion of the insulating layer, and a metal plug directly on the source/drain region of the thin-film transistor and the semiconductor plug and extending through at least a portion of the insulating layer. Related methods are also discussed.

摘要翻译： 静态随机存取存储器（SRAM）器件可以包括在其中具有源极/漏极区域的半导体衬底上的体MOS晶体管，体MOS晶体管上的绝缘层，以及在其中具有源极/漏极区域的薄膜晶体管 在体MOS晶体管上方的绝缘层上。 器件还可以包括在体MOS晶体管和薄膜晶体管之间的多层插头。 多层插头可以包括直接在体MOS晶体管的源极/漏极区域上并延伸穿过绝缘层的至少一部分的半导体插头，以及直接在薄膜的源极/漏极区域上的金属插塞 晶体管和半导体插头并延伸穿过绝缘层的至少一部分。 还讨论了相关方法。

公开(公告)号：US20050106838A1

公开(公告)日：2005-05-19

申请号：US10967374

申请日：2004-10-18

申请人： Hoon Lim ,  Soon-Moon Jung ,  Won-Seok Cho

发明人： Hoon Lim ,  Soon-Moon Jung ,  Won-Seok Cho

IPC分类号： H01L21/335 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/76

CPC分类号： H01L21/823481 ,  H01L21/823418

摘要： Semiconductor devices and methods of fabricating semiconductor devices that include a substrate and a device isolation layer in the substrate that defines an active region of the substrate are provided. The device isolation layer has a vertically protruding portion having a sidewall that extends vertically beyond a surface of the substrate. An epitaxial layer is provided on the surface of the substrate in the active region and extends onto the device isolation layer. The epitaxial layer is spaced apart from the sidewall of the vertically protruding portion of the device isolation layer. A gate pattern is provided on the epitaxial layer and source/drain regions are provided in the epitaxial layer at opposite sides of the gate pattern.

摘要翻译： 提供制造半导体器件的半导体器件和方法，其包括限定衬底的有源区的衬底中的衬底和器件隔离层。 器件隔离层具有垂直突出部分，其具有垂直延伸超出衬底表面的侧壁。 在有源区中的衬底的表面上提供外延层并延伸到器件隔离层上。 外延层与器件隔离层的垂直突出部分的侧壁间隔开。 在外延层上提供栅极图案，并且在栅极图案的相对侧的外延层中设置源极/漏极区域。

公开(公告)号：US20050029664A1

公开(公告)日：2005-02-10

申请号：US10932416

申请日：2004-09-02

申请人： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

发明人： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

IPC分类号： G11C11/412 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/76802 ,  H01L21/76895 ,  H01L27/1104

摘要： An interconnection structure is provided by forming a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode. The first active area, the first conductive line and/or the first electrode connected to the second active area, the second conductive line and/or the second electrode by the first damascene interconnect structure may be different from the first active area, the first conductive line and/or the first electrode and the second active area, the second conductive line and/or the second electrode connected by the second damascene interconnect structure.

摘要翻译： 通过形成第一镶嵌互连结构来提供互连结构，所述第一镶嵌互连结构直接连接衬底中的第一有源区，衬底上的第一导电线和/或衬底上的第一电极，在衬底中具有第二有源区， 导电线和/或基板上的第二电极。 第二镶嵌互连结构可以将第一有源区，第一导线和/或第一电极直接连接到第二有源区，第二导线和/或第二电极。 第一有源区域，第一导电线路和/或连接到第二有源区域的第一电极，第一导电线路和/或第二电极通过第一镶嵌互连结构可以不同于第一有源区域，第一导电 线路和/或第一电极和第二有源区域，第二导电线路和/或第二电极通过第二镶嵌互连结构连接。