Low surfactant, high sugar bars
    63.
    发明授权
    Low surfactant, high sugar bars 有权
    低表面活性剂,高糖酒吧

    公开(公告)号:US06841524B1

    公开(公告)日:2005-01-11

    申请号:US10682698

    申请日:2003-10-09

    CPC classification number: C11D3/221 C11D3/222 C11D9/262

    Abstract: The present composition comprises bar having small amounts of surfactant and high amounts of sugars which bar maintains good rates of wear and foams adequately. The sugar has unexpectedly been found to structure bars, even when little or no insoluble fatty acid is used, without degrading bar properties.

    Abstract translation: 本发明的组合物包含具有少量表面活性剂和大量糖的棒,其中棒保持良好的磨损率和充分的泡沫。 即使在使用少量或不溶性脂肪酸的情况下,糖也意外地被发现为结构条,而不降低酒吧性质。

    System and method for multiple store buffer forwarding in a system with a restrictive memory model
    64.
    发明授权
    System and method for multiple store buffer forwarding in a system with a restrictive memory model 有权
    具有限制性内存模型的系统中多存储缓冲区转发的系统和方法

    公开(公告)号:US06678807B2

    公开(公告)日:2004-01-13

    申请号:US09740803

    申请日:2000-12-21

    CPC classification number: G06F9/3826 G06F9/3834

    Abstract: The present invention relates to the use of multiple store buffer forwarding in a microprocessor system with a restrictive memory model. In accordance with an embodiment of the present invention, the system and method allow load operations that are completely covered by two or more store operations to receive data via store buffer forwarding in such a manner as to retain the side effects of the restrictive memory model thereby increasing processor performance without violating the restrictive memory model. In accordance with an embodiment the present invention, a method for multiple store buffer forwarding in a system with a restrictive memory model includes executing multiple store instructions, executing a load instruction, determining that a memory region addressed by the load instruction matches a cacheline address in a memory, determining that data stored by the multiple store instructions completely covers the memory region addressed by the load instruction, and transmitting a store forward is OK signal.

    Abstract translation: 本发明涉及在具有限制性存储器模型的微处理器系统中使用多存储缓冲器转发。 根据本发明的实施例,系统和方法允许由两个或多个存储操作完全覆盖的加载操作以经由存储缓冲器转发来接收数据,从而保持限制性存储器模型的副作用 提高处理器性能而不违反限制性内存模式。 根据本发明的实施例,一种用于具有限制性存储器模型的系统中的多存储缓冲器转发的方法包括执行多个存储指令,执行加载指令,确定由加载指令寻址的存储器区域与缓存线地址匹配 存储器,确定由多个存储指令存储的数据完全覆盖由加载指令寻址的存储器区域,并且向前发送存储区是OK信号。

    Multiple load miss handling in a cache memory system
    65.
    发明授权
    Multiple load miss handling in a cache memory system 有权
    高速缓冲存储器系统中的多次错误处理

    公开(公告)号:US06269427B1

    公开(公告)日:2001-07-31

    申请号:US09271493

    申请日:1999-03-18

    Abstract: A cache memory system including a cache memory configured for coupling to a load/store unit of a CPU, a buffer unit coupled to said cache memory, and an operation queue comprising a plurality of entries, wherein each valid operation queue entry points to an entry in the buffer unit. The buffer unit includes a plurality of data buffers and each of the data buffers is associated with a corresponding address tag. The system is configured to initiate a data fetch transaction and allocate an entry in the buffer unit in response to a CPU load operation that misses in both the cache memory and the buffer unit. The cache system is further configured to allocate entries in the operation queue in response to subsequent CPU load operations that miss in the cache memory but hit in the buffer unit prior to completion of the data fetch. Preferably, the system is configured to store the fetched data in the buffer unit entry upon satisfaction of said data fetch and still further configured to satisfy pending load operations in the operation queue from the buffer unit entry. In the preferred embodiment, the system is configured to reload the. cache memory from the buffer unit entry upon satisfying all operation queue entries pointing to the buffer unit entry and, thereafter, to invalidate the buffer unit entry and the operation queue entries. The buffer unit entries preferably each include data valid bits indicative of which portions of data stored in a buffer unit entry are valid.

    Abstract translation: 一种高速缓冲存储器系统,包括被配置为耦合到CPU的加载/存储单元的高速缓存存储器,耦合到所述高速缓存存储器的缓冲器单元和包括多个条目的操作队列,其中每个有效操作队列入口指向条目 在缓冲单元中。 缓冲单元包括多个数据缓冲器,并且每个数据缓冲器与相应的地址标签相关联。 该系统被配置为响应于在高速缓冲存储器和缓冲器单元中丢失的CPU加载操作而发起数据提取事务并在缓冲器单元中分配条目。 高速缓存系统还被配置为响应于在高速缓冲存储器中错过的随后的CPU加载操作来在操作队列中分配条目,而在数据提取完成之前在缓冲器单元中命中。 优选地,系统被配置为在满足所述数据提取时将获取的数据存储在缓冲器单元条目中,并且还被配置为满足来自缓冲器单元条目的操作队列中的未决加载操作。 在优选实施例中,系统被配置为重新加载。 满足指向缓冲单元条目的所有操作队列条目,然后使缓冲单元条目和操作队列条目无效,从缓冲单元条目缓存存储器。 缓冲单元条目优选地每个都包括指示存储在缓冲单元条目中的数据的哪些部分有效的数据有效位。

    In-shower lotion compositions comprising up to 10% free fatty acids wherein ratio of unsaturated to saturated fatty acids is at least 1:1
    68.
    发明授权
    In-shower lotion compositions comprising up to 10% free fatty acids wherein ratio of unsaturated to saturated fatty acids is at least 1:1 失效
    包含高达10%游离脂肪酸的淋浴洗剂组合物,其中不饱和脂肪酸与饱和脂肪酸的比例至少为1:1

    公开(公告)号:US08691197B2

    公开(公告)日:2014-04-08

    申请号:US11850144

    申请日:2007-09-05

    Abstract: This invention relates to rinse-off skin conditioning compositions comprising relatively low amounts of oil/emollient and relatively low amounts of aqueous phase stabilizer/structurant. Use of unsaturated fatty acid (or at least minimum amount of unsaturated fatty acid as percentage of total fatty acid) has been found to result in unexpectedly high hydration. In a second embodiment, use of branched fatty acid (at minimum amount branched as percentage of total) also results in superior hydration. Also mixtures of unsaturated and branched fatty acids can be used.In a second embodiment, the invention relates to method of enhancing hydration using compositions as noted.

    Abstract translation: 本发明涉及包含相对低量的油/润肤剂和相对低量的水相稳定剂/结构剂的漂洗皮肤调理组合物。 已经发现使用不饱和脂肪酸(或至少最少量的不饱和脂肪酸占总脂肪酸的百分比)导致意想不到的高水合作用。 在第二个实施方案中,使用支链脂肪酸(最小量分支占总量的百分比)也导致优异的水合作用。 还可以使用不饱和和支链脂肪酸的混合物。 在第二个实施方案中,本发明涉及使用如上所述的组合物来增强水合的方法。

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