公开(公告)号：US5129015A

公开(公告)日：1992-07-07

申请号：US511245

申请日：1990-04-19

Applicant: James D. Allen ,  Steve M. Blonstein

Inventor： James D. Allen ,  Steve M. Blonstein

IPC: H04N1/41 ,  G06F7/78 ,  G06F17/14 ,  G06T9/00 ,  G11C8/12 ,  G11C19/00 ,  H04N7/26 ,  H04N7/30 ,  H04N11/04

CPC classification number: G06F7/78 ,  G06F17/147 ,  G11C19/00 ,  G11C8/12 ,  H04N11/044 ,  H04N19/126 ,  H04N19/124 ,  H04N19/60

Abstract: Transforms such as the DCT are useful for image compression. One close relative of the DCT is preferred for its arithmetic simplicity. A method is described whereby the image compression is done with no multiplications. Other enhancements are made to improve image quality.

Abstract translation: 像DCT这样的变换对于图像压缩是有用的。 DCT的一个紧密相对于其算术简单性是优选的。 描述了一种方法，由此在不进行乘法的情况下完成图像压缩。 进行其他改进以提高图像质量。

公开(公告)号：US4994907A

公开(公告)日：1991-02-19

申请号：US399105

申请日：1989-08-28

Applicant: James D. Allen

Inventor： James D. Allen

IPC: G02B5/20 ,  H04N1/48 ,  H04N5/372

CPC classification number: H04N3/1581 ,  H04N1/486 ,  H04N3/1525

Abstract: A line sensor with photosites accurately located for color scanning. The sensor includes a plurality of photosites arranged in a two-dimensional, staggered pattern which is repeated across the length of the sensor. Only one photosite is located for every direction perpendicular to the axis of the line image. Individual color filters extend over all the photosites located at the same perpendicular distance from the line image axis. In one embodiment, the filters are disposed on separate transparent members which are aligned and assembled over the photosites.

Abstract translation: 具有准确定位用于彩色扫描的光斑的线传感器。 该传感器包括以二维交错图案布置的多个光电子，其跨过传感器的长度重复。 对于垂直于线图像轴线的每一个方向，只能定位一个照片。 单独的滤色器延伸到位于距离线图像轴线相同垂直距离的所有照片上。 在一个实施例中，过滤器设置在分开的透明构件上，所述透明构件对准并组装在光斑上。

公开(公告)号：US4475086A

公开(公告)日：1984-10-02

申请号：US364110

申请日：1982-03-31

Applicant: James D. Allen

Inventor： James D. Allen

IPC: G01R29/027 ,  H03K5/26 ,  H03K5/05

CPC classification number: G01R29/0273

Abstract: Apparatus is disclosed for determining whether the duty cycle of a periodic signal produced by an incremental encoder is within a predetermined acceptable range. The apparatus includes an oscillator which produces clock pulses at a substantially higher frequency than the periodic signal and a counter which is effective during a selected period of the periodic signal to add the number of clock pulses produced during that portion of the period when the square wave signal is high and subtract from the accumulated number, the number of clock pulses produced when the signal is low. A detector, in response to the final number held by the counter, determines whether the duty cycle is within the predetermined acceptable range.

Abstract translation: 公开了用于确定由增量编码器产生的周期信号的占空比是否在预定的可接受范围内的装置。 该装置包括以比周期信号更高的频率产生时钟脉冲的振荡器和在周期信号的选定周期期间有效的计数器，以增加在该方波的该部分期间产生的时钟脉冲数 信号为高电平，并从累加数减去信号低时产生的时钟脉冲数。 响应于由计数器保持的最终数量，检测器确定占空比是否在预定的可接受范围内。

公开(公告)号：US08850165B2

公开(公告)日：2014-09-30

申请号：US13155055

申请日：2011-06-07

Applicant: David W. Burns ,  James D. Allen ,  Michael D. Upton ,  Darrell D. Boggs ,  David J. Sager

Inventor： David W. Burns ,  James D. Allen ,  Michael D. Upton ,  Darrell D. Boggs ,  David J. Sager

IPC: G06F9/38 ,  G06F9/48

CPC classification number: G06F9/4881 ,  G06F9/3851

Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.

Abstract translation: 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。

公开(公告)号：US20140281197A1

公开(公告)日：2014-09-18

申请号：US13997437

申请日：2013-03-15

Applicant: Jose S. Niell ,  Daniel F. Cutter ,  James D. Allen ,  Deepak Limaye ,  Shadi T. Khasawneh

Inventor： Jose S. Niell ,  Daniel F. Cutter ,  James D. Allen ,  Deepak Limaye ,  Shadi T. Khasawneh

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/1027 ,  Y02D10/13

Abstract: In one embodiment, a conflict detection logic is configured to receive a plurality of memory requests from an arbiter of a coherent fabric of a system on a chip (SoC). The conflict detection logic includes snoop filter logic to downgrade a first snooped memory request for a first address to an unsnooped memory request when an indicator associated with the first address indicates that the coherent fabric has control of the first address. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，冲突检测逻辑被配置为从芯片上的系统的相干结构（SoC）的仲裁器接收多个存储器请求。 当与第一地址相关联的指示符指示相干结构具有对第一地址的控制时，冲突检测逻辑包括窥探过滤器逻辑，以将第一地址的第一窥探存储器请求降级到未播放的存储器请求。 描述和要求保护其他实施例。

公开(公告)号：US08782719B2

公开(公告)日：2014-07-15

申请号：US11803649

申请日：2007-05-15

Applicant: Robert G. Arsenault ,  Raynold M. Kahn ,  Richard F. Purpura ,  Gilbert Zaldivar ,  James D. Allen

Inventor： Robert G. Arsenault ,  Raynold M. Kahn ,  Richard F. Purpura ,  Gilbert Zaldivar ,  James D. Allen

IPC: H04N7/173

CPC classification number: H04N7/162 ,  H04N7/17309 ,  H04N21/25875 ,  H04N21/4147 ,  H04N21/4312 ,  H04N21/4314 ,  H04N21/44222 ,  H04N21/4431 ,  H04N21/4524 ,  H04N21/4753 ,  H04N21/6187 ,  H04N2007/1739

Abstract: Methods and apparatuses for selectively displaying a video program are disclosed. A system for selectively displaying a video program in accordance with the present invention comprises a transmission station, including a server for attaching information to the video program, a plurality of satellites receiving at least an uplink signal which includes the information and the video program from the transmission station and producing a downlink signal based on the uplink signal, an antenna, the antenna receiving the downlink signal, and at least one receiver, coupled to the antenna, for receiving the downlink signal and interpreting the information in the downlink signal, wherein the at least one receiver selectively displays the video program based on at least the interpreted information.

Abstract translation: 公开了用于选择性地显示视频节目的方法和装置。 根据本发明的用于选择性地显示视频节目的系统包括：传输站，包括用于将信息附加到视频节目的服务器;多个卫星，其接收至少一个上行链路信号，该上行链路信号包括来自该信息的信息和视频节目 发送站，并且基于上行链路信号产生下行链路信号，天线，接收下行链路信号的天线和耦合到天线的至少一个接收机，用于接收下行链路信号并解释下行链路信号中的信息，其中， 至少一个接收器至少基于解释信息选择性地显示视频节目。

公开(公告)号：US08763059B1

公开(公告)日：2014-06-24

申请号：US11205249

申请日：2005-08-16

Applicant: Thomas H. James ,  Raynold M. Kahn ,  James D. Allen

Inventor： Thomas H. James ,  Raynold M. Kahn ,  James D. Allen

IPC: H04N7/173 ,  H04N7/20

CPC classification number: H04N7/20 ,  H04N7/106 ,  H04N21/6143 ,  H04N21/6168

Abstract: A method and apparatus for coupling an Integrated Receiver Decoder (IRD) to a telephone line via a coaxial cable used for delivering direct broadcast satellite signals to the IRD. One embodiment comprises a port coupler, coupled to a telephone line and to the coaxial cable, and a client unit, coupled between the port coupler and the IRD, wherein the port coupler connects the IRD to the direct broadcast satellite signals and connects the IRD to the phone line via the client unit, and at least satellite signals, satellite control signals, telephone data signals, and telephone system protocol signals travel on the coaxial cable between the client unit and the port coupler.

Abstract translation: 一种用于通过用于将直接广播卫星信号传送到IRD的同轴电缆将集成接收器解码器（IRD）耦合到电话线的方法和装置。 一个实施例包括耦合到电话线和同轴电缆的端口耦合器，以及耦合在端口耦合器和IRD之间的客户端单元，其中端口耦合器将IRD连接到直接广播卫星信号，并将IRD连接到 经由客户端单元的电话线，并且至少卫星信号，卫星控制信号，电话数据信号和电话系统协议信号在客户机单元和端口耦合器之间的同轴电缆上传播。

公开(公告)号：US20140068230A1

公开(公告)日：2014-03-06

申请号：US13977064

申请日：2012-10-04

Applicant: Venkateswara Madduri ,  Jonathan Combs ,  James E. Phillips ,  Stephen J. Robinson ,  James D. Allen ,  Jonathan J. Tyler

Inventor： Venkateswara Madduri ,  Jonathan Combs ,  James E. Phillips ,  Stephen J. Robinson ,  James D. Allen ,  Jonathan J. Tyler

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

Abstract: A computer system and processor for elimination of move operations include circuits that obtain a computer instruction and bypass execution units in response to determining that the instruction includes a move operation that involves a transfer of data from a logical source register to a logical destination register. Instead of executing the move operation, the transfer of the data is performed by tracking changes in data dependencies of the source and the destination registers, and assigning a physical register associated with the source register to the destination register based on the dependencies.

Abstract translation: 用于消除移动操作的计算机系统和处理器包括响应于确定该指令包括涉及将数据从逻辑源寄存器传送到逻辑目标寄存器的移动操作而获得计算机指令和旁路执行单元的电路。 代替执行移动操作，通过跟踪源和目的地寄存器的数据相关性的变化以及基于依赖性将与源寄存器相关联的物理寄存器分配给目的寄存器来执行数据的传送。

公开(公告)号：US20110239221A1

公开(公告)日：2011-09-29

申请号：US13155055

申请日：2011-06-07

Applicant: David W. Burns ,  James D. Allen ,  Michael D. Upton ,  Darrell D. Boggs ,  David J. Sager

Inventor： David W. Burns ,  James D. Allen ,  Michael D. Upton ,  Darrell D. Boggs ,  David J. Sager

IPC: G06F9/46

CPC classification number: G06F9/4881 ,  G06F9/3851

Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.

Abstract translation: 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。

公开(公告)号：US07987346B2

公开(公告)日：2011-07-26

申请号：US13011711

申请日：2011-01-21

Applicant: David Burns ,  James D. Allen ,  Michael D. Upton ,  Darrell D. Boggs ,  David J. Sager

Inventor： David Burns ,  James D. Allen ,  Michael D. Upton ,  Darrell D. Boggs ,  David J. Sager

IPC: G06F9/30

CPC classification number: G06F9/4881 ,  G06F9/3851

Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.

Abstract translation: 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。