公开(公告)号：US06990550B2

公开(公告)日：2006-01-24

申请号：US10283555

申请日：2002-10-30

申请人： Siegfried Kay Hesse ,  Dale E. Gulick

发明人： Siegfried Kay Hesse ,  Dale E. Gulick

IPC分类号： G06F13/20 ,  H04J3/16

CPC分类号： G06F13/1605

摘要： A USB (Universal Serial Bus) host controller, a corresponding integrated circuit chip, a computer system and an operation method are provided for handling the data traffic between at least one USB device and the computer system having system memory. A transaction processing unit processes transactions to or from the at least one USB device. Further, a transaction duration management unit is provided for determining estimated duration values of the transactions. The transaction processing unit is adapted to process the transactions dependent on the estimated duration values. A descriptor-to-transaction converter may be provided, and the prefetched mechanism may be made dependent on a threshold value relating to the estimated duration values.

公开(公告)号：US06952751B1

公开(公告)日：2005-10-04

申请号：US09544858

申请日：2000-04-07

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F13/36 ,  G06F13/42 ,  H04Q1/30

CPC分类号： G06F13/4208

摘要： A method and system for operating a bus according to a plurality of bus protocols, including a legacy bus protocol. A first signal is transmitted indicating a transaction request of a first kind. A second signal is transmitted indicating a transaction request of a second kind. The second signal may be decoded according to a plurality of protocols. The first signal is decoded prior to decoding the second signal. The decode of the first signal indicates which of the plurality of protocols should be used to decode the second signal. A computer system includes a bus, preferably an LPC bus, coupling two or more devices.

摘要翻译： 一种用于根据包括传统总线协议的多个总线协议来操作总线的方法和系统。 发送指示第一类的交易请求的第一信号。 发送指示第二种类型的交易请求的第二信号。 可以根据多个协议对第二信号进行解码。 第一信号在解码第二信号之前被解码。 第一信号的解码指示应该使用多个协议来解码第二信号。 计算机系统包括耦合两个或多个设备的总线，优选地是LPC总线。

公开(公告)号：US06944725B2

公开(公告)日：2005-09-13

申请号：US10283733

申请日：2002-10-30

申请人： Siegfried Kay Hesse ,  Dale E. Gulick

发明人： Siegfried Kay Hesse ,  Dale E. Gulick

IPC分类号： G06F3/06 ,  G06F12/00 ,  G06F13/00 ,  G06F13/38

CPC分类号： G06F13/385 ,  G06F3/0601 ,  G06F2003/0691 ,  G06F2213/0042

摘要： A data storage mechanism is provided where a plurality of data items are stored in a plurality of register elements. Each registered element is capable of storing at least one data item. The plurality of register elements is arranged to form a sequence of register elements. First data is stored in a first part of the sequence and second data is stored in a second part of the sequence. The first part and the second part are of variable lengths with the sum of the variable lengths being equal to the lengths of the sequence of register elements. Thus, a double-ended queue mechanism is provided which may be used to store data of different type or data which is either scheduled periodically or asynchronously. The mechanism may be used in a USB 2.0 compliant host controller.

摘要翻译： 提供了一种数据存储机制，其中多个数据项被存储在多个寄存器元件中。 每个注册的元素能够存储至少一个数据项。 多个寄存器元件被布置成形成寄存器元件的序列。 第一数据存储在序列的第一部分中，第二数据被存储在序列的第二部分中。 第一部分和第二部分是可变长度，其可变长度之和等于寄存器元件序列的长度。 因此，提供了一种双端口队列机制，其可以用于存储周期性地或异步地调度的不同类型或数据的数据。 该机制可用于兼容USB 2.0的主机控制器。

公开(公告)号：US06836813B1

公开(公告)日：2004-12-28

申请号：US09998758

申请日：2001-11-30

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F1336

CPC分类号： G06F13/4022 ,  G06F2213/0024 ,  G06F2213/0026

摘要： A switching I/O node for connection in a multiprocessor computer system. An input/output node switch includes a bridge unit and a packet bus switch unit implemented on an integrated circuit chip. The bridge unit may receive a plurality of peripheral transactions from a peripheral bus and may transmit a plurality of upstream packet transactions corresponding to the plurality of peripheral transactions. The packet bus switch may receive the upstream packet transactions on an internal point-to-point packet bus link and may determine a destination of each of the upstream packet transactions. The packet bus switch may further route selected ones of the upstream packet transactions to a first processor interface coupled to a first point-to-point packet bus link and route others of the upstream packet transactions to a second processor interface coupled to a second point-to-point packet bus link in response to determining the destination each of the upstream packet transactions.

摘要翻译： 用于在多处理器计算机系统中连接的交换I / O节点。 输入/输出节点开关包括在集成电路芯片上实现的桥单元和分组总线开关单元。 桥接单元可以从外围总线接收多个外围事务，并且可以发送与多个外围事务相对应的多个上行分组事务。 分组总线交换机可以在内部点对点分组总线链路上接收上行分组事务，并且可以确定每个上行分组事务的目的地。 分组总线交换机可以将上游分组事务中的选择的一个进一步路由到耦合到第一点对点分组总线链路的第一处理器接口，并将上游分组事务中的另一个路由到耦合到第二点到多个分组总线链路的第二处理器接口， 响应于确定每个上游分组事务的目的地，点对点分组总线链路。

公开(公告)号：US06823403B2

公开(公告)日：2004-11-23

申请号：US10184407

申请日：2002-06-27

申请人： Dale E. Gulick ,  Siegfried Kay Hesse

发明人： Dale E. Gulick ,  Siegfried Kay Hesse

IPC分类号： G06F1328

CPC分类号： G06F12/0879 ,  G06F13/28 ,  H04B7/0822

摘要： A DMA (Direct Memory Access) mechanism is provided that may be of improved performance in particular in connection with high-speed packet buses. A transmit DMA engine for outputting read requests for a memory interface and receiving requested data from the memory interface, comprises a data transfer initiating unit for outputting first address data identifying a first memory range. Further, a boundary alignment unit is provided for generating second address data using the first address data, where the second address data identifies a second memory range that differs from the first memory range in at least one boundary. Further a corresponding boundary alignment may be done in a receive DMA engine. The DMA mechanism may be performed in a USB-2 host controller that has HyperTransport capabilities.

摘要翻译： 提供了DMA（直接存储器访问）机制，其可以具有改进的性能，特别是与高速分组总线相关。 一种用于输出对存储器接口的读取请求并从存储器接口接收所请求的数据的发送DMA引擎，包括用于输出识别第一存储器范围的第一地址数据的数据传输启动单元。 此外，提供边界对齐单元，用于使用第一地址数据生成第二地址数据，其中第二地址数据标识与至少一个边界中的第一存储器范围不同的第二存储器范围。 此外，可以在接收DMA引擎中进行相应的边界对准。 DMA机制可以在具有HyperTransport功能的USB-2主机控制器中执行。

公开(公告)号：US06766347B1

公开(公告)日：2004-07-20

申请号：US09094168

申请日：1998-06-09

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F900

CPC分类号： G01R33/54

摘要： A computer system includes a real-time interrupt that causes the operating system to determine which isochronous tasks are pending. In one embodiment, applications that include isochronous tasks are certified to be well-behaved and the operating system will only initiate applications that are known to be well-behaved by checking a list of certified applications. The operating system will not initiate an application if insufficient resources are available for executing the tasks of the application. Each application informs the operating system of an execution rate and a maximum duration of its isochronous tasks. Prior to initiating an application, the operating system verifies that resources are available to execute the isochronous tasks of the application. The operating system includes a non-maskable interrupt to terminate isochronous tasks. Termination may be necessary if an isochronous task fails to execute within its specified maximum duration. Alternatively, an isochronous task may be preempted to execute a higher priority task. The operating system may include two types of time-slices. Higher priority tasks are allocated to quick slices and lower priority tasks are allocated to standard slices. Standard slices are preemptable and quick slices are not preemptable.

摘要翻译： 计算机系统包括使操作系统确定哪个等时任务正在等待的实时中断。 在一个实施例中，包括同步任务的应用被认证为良好的操作，并且操作系统将仅通过检查认证应用的列表来启动已知具有良好行为的应用。 如果没有足够的资源可用于执行应用程序的任务，操作系统将不会启动应用程序。 每个应用程序通知操作系统其同步任务的执行速率和最大持续时间。 在启动应用程序之前，操作系统会验​​证资源是否可用来执行应用程序的同步任务。 操作系统包括一个不可屏蔽的中断来终止同步任务。 如果同步任务在其指定的最大持续时间内无法执行，则可能需要终止。 或者，可以抢占同步任务来执行较高优先级的任务。 操作系统可以包括两种类型的时间片。 较高优先级的任务分配给快速切片，较低优先级的任务分配给标准切片。 标准切片是可抢占的，快速切片是不可抢占的。

公开(公告)号：US06690676B1

公开(公告)日：2004-02-10

申请号：US09330635

申请日：1999-06-11

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F1314

CPC分类号： G06F13/36

摘要： The protocol of a multi-pipe interconnection bus includes the ability to send a non-addressed read or write transaction request over one of the pipes of a multiple-pipe computer interconnect bus. The multiple pipes carry transactions on a packet multiplexed basis. The transaction request is sent over one of the pipes from a source to a target and includes a non-addressed transaction command. The transaction is performed in a predetermined location in response to the non-addressed transaction command. A transaction response is returned upon completion of the transaction.

摘要翻译： 多管互连总线的协议包括通过多管计算机互连总线的管道之一发送非寻址读或写事务请求的能力。 多个管道以分组复用为基础进行事务处理。 事务请求通过一个管道从源发送到目标，并且包括未寻址的事务命令。 响应于未寻址的事务命令，在预定位置执行事务。 交易完成后返回事务响应。

公开(公告)号：US06671748B1

公开(公告)日：2003-12-30

申请号：US09904374

申请日：2001-07-11

申请人： Terry Lynn Cole ,  Dale E. Gulick ,  Timothy C. Maleck ,  Frank Barth ,  Joerg Winkler

发明人： Terry Lynn Cole ,  Dale E. Gulick ,  Timothy C. Maleck ,  Frank Barth ,  Joerg Winkler

IPC分类号： G06F1300

CPC分类号： G06F13/387

摘要： A method and apparatus for passing device configuration information to a shared controller. In one embodiment, a host controller may be configured to read configuration from one or more peripheral devices coupled to a serial bus. The peripheral devices may include coder/decoder (codec) circuitry, and may be implemented using a riser card. The host controller may employ one or more of several different techniques in order to read configuration information from the peripheral device. The configuration information at a minimum includes a device identifier, which may identify the vendor and the function of the device. Additional information needed to configure the device to communicate over the peripheral bus may also be obtained with a read of the device, or various lookup mechanisms, such as a lookup table or a tree-like data structure. After configuration information has been obtained for each device coupled to the bus, the host controller may dynamically configure each of the devices for communication over the bus, thereby allowing the flexibility to enumerate riser cards and add new functions through peripheral devices to the computer system in which the bus is implemented.

摘要翻译： 一种用于将设备配置信息传递到共享控制器的方法和装置。 在一个实施例中，主机控制器可以被配置为从耦合到串行总线的一个或多个外围设备读取配置。 外围设备可以包括编码器/解码器（编解码器）电路，并且可以使用转接卡来实现。 主机控制器可以采用几种不同技术中的一种或多种，​​以便从外围设备读取配置信息。 配置信息至少包括设备标识符，其可以标识供应商和设备的功能。 通过设备的读取或诸如查找表或树状数据结构的各种查找机制也可以获得将设备配置成通过外围总线进行通信所需的附加信息。 在针对耦合到总线的每个设备获得配置信息之后，主机控制器可以动态地配置每个设备以通过总线进行通信，从而允许灵活地枚举转接卡并且通过外围设备将新功能添加到计算机系统 总线实施。

公开(公告)号：US06336179B1

公开(公告)日：2002-01-01

申请号：US09137345

申请日：1998-08-21

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F1500

CPC分类号： G06F13/28

摘要： A first counter sequentially counts a plurality of numbers from respective sources requesting transfer of data. Each of the numbers represents an amount of isochronous data to transfer over the bus from the respective ones of the sources during a frame on a bus. A count value in a second counter is selectably incremented when the first counter is counting, to provide a remaining count value indicative a remaining amount of data to transfer during the frame. The remaining count value in the second counter is decremented for each isochronous transfer on the bus after the remaining amount of data to transfer has been determined from all sources requesting transfer of isochronous data during the frame. A third counter tracks the time remaining in the frame and compares the remaining count value to the time remaining in the frame to determine a priority mode on the bus. The bus switches to isochronous priority mode on the bus according to a comparison of the remaining count value and the time remaining in the time period.

摘要翻译： 第一计数器从请求传送数据的各个源顺序地计数多个数字。 每个数字表示在总线上的帧期间通过总线从相应的源传送的同步数据量。 当第一计数器正在计数时，第二计数器中的计数值可选地增加，以提供指示在帧期间传送的数据的剩余量的剩余计数值。 在从框架中请求传输同步数据的所有来源确定要传输的剩余数据量之后，在总线上的每个等时传输中，第二计数器中的剩余计数值递减。 第三个计数器跟踪帧中的剩余时间，并将剩余计数值与帧中的剩余时间进行比较，以确定总线上的优先模式。 根据剩余计数值与时间段剩余时间的比较，总线上总线切换到总线上的等时优先模式。

公开(公告)号：US06263385B1

公开(公告)日：2001-07-17

申请号：US08955327

申请日：1997-10-20

申请人： Dale E. Gulick ,  David Neal Suggs

发明人： Dale E. Gulick ,  David Neal Suggs

IPC分类号： G06F1300

CPC分类号： G06F13/4004

摘要： A first and second integrated circuit contain respectively a first and second portion of a parallel port, the first portion includes control, configuration, data and status registers and the second portion includes parallel port input and output terminals. A bus couples the first and second integrated circuits and transfers parallel port control and data information between the first and second integrated circuits. The bus includes a clock line providing a clock signal. The bus also includes a data out line that serially transfers output control and data bits from the first to the second integrated circuit, the data and control bits to be provided to the parallel port output terminals on the second integrated circuit. The bus also includes a data in line providing input data and control information from the terminals of the parallel port to the first integrated circuit. The bus provides data either substantially continuously in frames defined by a frame sync or uses a start bit to go from an idle state to a data transfer state according to the read and write operations of the parallel port. The mode of operation of the parallel port determines whether data is transferred continuously in frames or after a start bit.

摘要翻译： 第一和第二集成电路分别包含并行端口的第一和第二部分，第一部分包括控制，配置，数据和状态寄存器，第二部分包括并行端口输入和输出端子。 总线耦合第一和第二集成电路，并且在第一和第二集成电路之间传送并行端口控制和数据信息。 总线包括提供时钟信号的时钟线。 总线还包括从第一至第二集成电路串行传输输出控制和数据位的数据输出线，将要提供给第二集成电路上的并行端口输出端的数据和控制位。 该总线还包括一行数据，提供从并行端口到第一集成电路的端子的输入数据和控制信息。 总线基本上连续地在由帧同步定义的帧中提供数据，或者根据并行端口的读取和写入操作，使起始位从空闲状态变为数据传输状态。 并行端口的操作模式确定数据是以帧为单位还是在起始位之后连续传输。