摘要:
A method and apparatus are disclosed for performing adaptive memory power management in a system employing a CPU and a memory subsystem. A CPU throttle control (THR) module generates a CPU throttle control signal indicating when the CPU is idle. A memory controller (MC) module generates memory power management signals based on at least one of the CPU throttle control signal, memory read/write signals, memory access break events, and bus master access requests. Certain portions of the memory subsystem are powered down in response to the memory power management signals. Memory power management is performed on a time segment by time segment basis to achieve efficient power management of the memory subsystem during CPU run time.
摘要:
Aspects of the invention provide a method and system for securely managing the storage and retrieval of data. Securely managing the storage and retrieval of data may include receiving a first disaster recovery code and acquiring a first password corresponding to the first disaster recovery code. A first disaster recovery key may be generated based on the first disaster recovery code and the first password. Another aspect of the invention may also include generating the received first disaster recovery code based on said first password and the first disaster recovery key. The generated disaster recovery code may be securely stored on at least a portion of a storage device or a removable media. Data stored on the storage device may be encrypted using the first generated disaster recovery key. Additionally, data read from the storage device may be decrypted using the generated first disaster recovery key.
摘要:
Aspects of the invention provide a method and system for securely managing the storage and retrieval of data. Securely managing the storage and retrieval of data may include receiving a first disaster recovery code and acquiring a first password corresponding to the first disaster recovery code. A first disaster recovery key may be generated based on the first disaster recovery code and the first password. Another aspect of the invention may also include generating the received first disaster recovery code based on said first password and the first disaster recovery key. The generated disaster recovery code may be securely stored on at least a portion of a storage device or a removable media. Data stored on the storage device may be encrypted using the first generated disaster recovery key. Additionally, data read from the storage device may be decrypted using the generated first disaster recovery key.
摘要:
In accordance with a method for wireless communication, in a coexistence system comprising a plurality of different wireless interface devices within a single integrated circuit, wherein each of the plurality of wireless interface devices utilizes a corresponding different wireless communication standard, and when one of the plurality of wireless interface devices is receiving or will receive a packet, communicating from the one of the plurality of wireless interface devices, an indication to at least one of a remaining one or remaining ones of the plurality of wireless interface devices, which enables the at least one of the remaining one or ones of the plurality of wireless interface devices to delay corresponding transmission based on the indication. The indication may include status information for the receiving of the packet by the one of the plurality of wireless interface devices.
摘要:
A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.
摘要:
A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.
摘要:
Various aspects of the invention provide a plurality of systems and methods of selectively enabling access to data stored in a data storage device, by one or more data processing devices communicatively coupled to the data storage device. In a representative embodiment, selective access to one or more data pools may be made as a function of one or more interfaces of the data storage device. In a representative embodiment, selective access to one or more data pools may be made as a function of one or more data file types associated with one or more data pools of the data storage device. In a representative embodiment, access to data stored in one or more data pools of the data storage device may be based on or associated with one or more types networks associated with the data storage device.
摘要:
A method and system is provided for instrumenting a program by optimizing probe insertion. The number of probe insertions into instrumented code is reduced by providing optimal probe insertion points. The control flow of the code is analyzed along with the arc and block relationships to build a post-dominator tree. An optimization map is generated from the post-dominator tree that provides the optimal probe insertion points. Once the probes are inserted and data is collected by running the binary representing the code and probes, the data may be overlaid onto the optimization map and arc and block relationships to provide code coverage data.
摘要:
A method and apparatus are disclosed for performing adaptive run-time power management in a system employing a CPU and an operating system. A CPU cycle tracker (CCT) module monitors critical CPU signals and generates CPU performance data based on the critical CPU signals. An adaptive CPU throttler (THR) module uses the CPU performance data, along with a CPU percent idle value fed back from the operating system, to generate a CPU throttle control signal during predefined run-time segments of the CPU run time. The CPU throttle control signal links back to the CPU and adaptively adjusts CPU throttling and, therefore, power usage of the CPU during each of the run-time segments.
摘要:
One or more systems and methods are disclosed to securely authenticate one or more wireless communication devices using a subscriber identification mechanism provided by a wireless communication device. The subscriber identification mechanism provides one or more keys and algorithms used in the authentication of a wireless communication device. In one embodiment, the subscriber identification mechanism comprises a subscriber identity module (SIM) card capable of being easily inserted into a wireless communication device. In one embodiment, wireless signal transmission occurs over a GSM/GPRS/EDGE network.