公开(公告)号：US20080191246A1

公开(公告)日：2008-08-14

申请号：US11673645

申请日：2007-02-12

申请人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh

发明人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh

IPC分类号： H01L21/8249 ,  H01L21/331 ,  H01L29/737

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7378 ,  Y10S438/969

摘要： The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.

摘要翻译： 本发明在一个方面提供了一种用于制造半导体器件的方法，其包括通过发射极层中的开口进行蚀刻以从暴露掺杂的皿的下面的氧化物层形成空腔。 通过调整工艺参数以在第一SiGe层中引起应变，在空腔内和掺杂槽之上形成其中具有Ge浓度的第一硅/锗（SiGe）层。 在第一SiGe层上形成第二SiGe层，并且在第二SiGe层上形成覆盖层。

公开(公告)号：US20070278539A1

公开(公告)日：2007-12-06

申请号：US11446016

申请日：2006-06-02

申请人： Mark Victor Dyson ,  Nace Rossi ,  Ranbir Singh

发明人： Mark Victor Dyson ,  Nace Rossi ,  Ranbir Singh

IPC分类号： H01L29/76 ,  H01L29/808 ,  H01L21/337

CPC分类号： H01L29/66242 ,  H01L27/0248 ,  H01L29/66901 ,  H01L29/7378 ,  H01L29/808

摘要： A semiconductor device is described that operates as an improved junction field effect transistor (JFET). A bipolar transistor with a collector region, a base region, an emitter region, a first base contact, and a second base contact insulated from the first base contact, has the base region lightly doped to about a 1E16 to 5E17 atoms/cm3 doping level. A connection is provided between the emitter region and the collector region to act as a JFET gate contact for the bipolar transistor. The semiconductor device operates as an improved JFET with the first base contact being a drain contact and the second base contact being a source contact. A method for manufacture of an improved JFET on a chip containing conventional bipolar devices is also described. The improved JFET is shown being used with a write head in a disk drive system for providing electrostatic discharge protection.

摘要翻译： 描述了作为改进的结型场效应晶体管（JFET）工作的半导体器件。 具有集电极区域，基极区域，发射极区域，第一基极触点和与第一基极接触绝缘的第二基极触点的双极晶体管具有轻度掺杂到约1E16至5E17原子/ cm 2的基极区域 > 3 掺杂水平。 在发射极区域和集电极区域之间提供连接以用作双极晶体管的JFET栅极接触。 半导体器件作为改进的JFET工作，第一基极触点是漏极触点，第二基极触点是源极触点。 还描述了用于制造包含常规双极器件的芯片上的改进的JFET的方法。 改进的JFET被示出用于提供静电放电保护的盘驱动系统中的写头。

公开(公告)号：US20070274126A1

公开(公告)日：2007-11-29

申请号：US10586176

申请日：2004-01-23

申请人： Ross Kohler ,  Richard McPartland ,  Ranbir Singh

发明人： Ross Kohler ,  Richard McPartland ,  Ranbir Singh

IPC分类号： G11C16/04 ,  H01L29/78

CPC分类号： G11C17/14 ,  H01L27/112

摘要： One time programmable memory devices are disclosed that are programmed using hot carrier induced degradation to alter one or more transistors characteristics. A one time programmable memory device is comprised of an array of transistors. Transistors in the array are selectively programmed using hot carrier induced changes in one or more transistor characteristics, such as changes to the saturation current, threshold voltage or both, of the transistors. The changes to the transistor characteristics are achieved in a similar manner to known hot carrier transistor aging principles. The disclosed one time programmable memory devices are small and programmable at low voltages and small current.

摘要翻译： 公开了一次可编程存储器件，其使用热载流子诱导劣化来编程以改变一个或多个晶体管特性。 一次可编程存储器件由晶体管阵列组成。 阵列中的晶体管使用热载流子引起的一个或多个晶体管特性的改变（例如晶体管的饱和电流，阈值电压或两者的改变）来选择性地编程。 以与已知的热载流子晶体管老化原理相似的方式实现晶体管特性的变化。 所公开的一次可编程存储器件小，可在低电压和小电流下编程。

公开(公告)号：US20070066074A1

公开(公告)日：2007-03-22

申请号：US11230188

申请日：2005-09-19

申请人： Nace Rossi ,  Ranbir Singh ,  Arun Nanda

发明人： Nace Rossi ,  Ranbir Singh ,  Arun Nanda

IPC分类号： H01L29/00 ,  H01L21/302 ,  H01L21/311

CPC分类号： H01L21/31116 ,  H01L21/76205 ,  H01L21/76232

摘要： A shallow trench isolation structure having a negative taper angle and a method for forming same. A silicon nitride layer formed over a semiconductor substrate is etched according to a plasma etch process to form a first opening therein having sidewalls that present a negative taper angle. The substrate is etched to form a trench therein underlying the first opening. Silicon dioxide fills both the opening and the trench to form the shallow trench isolation structure, with the silicon dioxide in the opening exhibiting a negative taper angle to avoid formation of conductive stringers during subsequent process steps.

摘要翻译： 具有负锥角的浅沟槽隔离结构及其形成方法。 根据等离子体蚀刻工艺蚀刻形成在半导体衬底上的氮化硅层，以形成其中具有负锥角的侧壁的第一开口。 蚀刻衬底以在第一开口下方形成沟槽。 二氧化硅填充开口和沟槽以形成浅沟槽隔离结构，其中开口中的二氧化硅呈现负锥角，以避免在随后的工艺步骤期间形成导电条。

公开(公告)号：US07141486B1

公开(公告)日：2006-11-28

申请号：US11153893

申请日：2005-06-15

申请人： Nace Rossi ,  Ranbir Singh ,  Arun K. Nanda

发明人： Nace Rossi ,  Ranbir Singh ,  Arun K. Nanda

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： A shallow trench isolation structure having a negative taper angle. A graded doped sacrificial layer is formed over a semiconductor substrate and etched to form a first trench therein having trench sidewalls that present a negative taper angle. The substrate is also etched to form a second trench therein overlying the first trench. Silicon dioxide fills both the first and the second trenches to form the shallow trench isolation structure, with the silicon dioxide in the first trench exhibiting a negative taper angle to avoid formation of polysilicon stringers during a gate polysilicon deposition.

摘要翻译： 具有负锥角的浅沟槽隔离结构。 梯度掺杂牺牲层形成在半导体衬底之上，并被蚀刻以形成其中具有呈负锥度角的沟槽侧壁的第一沟槽。 衬底也被蚀刻以在其中覆盖第一沟槽上形成第二沟槽。 二氧化硅填充第一和第二沟槽两者以形成浅沟槽隔离结构，其中第一沟槽中的二氧化硅呈现负锥角，以避免在栅极多晶硅沉积期间形成多晶硅桁条。

公开(公告)号：US07002829B2

公开(公告)日：2006-02-21

申请号：US10675571

申请日：2003-09-30

申请人： Ranbir Singh ,  Richard J. McPartland ,  Ross A. Kohler

发明人： Ranbir Singh ,  Richard J. McPartland ,  Ross A. Kohler

IPC分类号： G11C17/00

CPC分类号： G11C17/18

摘要： A method and apparatus for opening a fuse formed on a semiconductor substrate. The apparatus comprises a thyristor formed from CMOS device regions and having a one or two control terminals for permitting current to flow through the thyristor into the fuse, for opening the fuse.

摘要翻译： 一种用于打开形成在半导体衬底上的熔丝的方法和装置。 该装置包括由CMOS器件区形成并具有一个或两个控制端子的晶闸管，用于允许电流流过晶闸管进入保险丝，用于打开保险丝。

公开(公告)号：US20050269633A1

公开(公告)日：2005-12-08

申请号：US10859565

申请日：2004-06-03

申请人： Ranbir Singh

发明人： Ranbir Singh

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H03K5/153 ,  H03K5/22

CPC分类号： H01L29/7825 ,  H01L29/0657 ,  H01L29/1087 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42372

摘要： A lateral drift vertical metal-insulated field effect transistor (LDVMISFET) with an optimum conducting channel formed in Silicon Carbide, is provided as a power transistor with a voltage rating of greater than 200V. The lateral drift region achieves a better on-resistance/breakdown voltage trade-off than the conventional vertical drift region design of power MOSFETs. This is achieved by using an optimal doping and thickness for the voltage blocking and current conduction. The drain and backside terminal is able to support at least the rated blocking voltage of the device. A vertical MIS channel may be formed on the favorable 11-20 plane to achieve a higher MIS channel mobility as compared to the conventional 0001 or 000-1 planes resulting in a much lower on-resistance for the same blocking voltage as compared to conventional vertical MOSFET with similar blocking voltage.

摘要翻译： 提供具有在碳化硅中形成的最佳导电沟道的横向漂移垂直金属绝缘场效应晶体管（LDVMISFET）作为额定功率大于200V的功率晶体管。 横向漂移区域实现了比功率MOSFET的常规垂直漂移区域设计更好的导通电阻/击穿电压权衡。 这通过使用最佳掺杂和厚度来实现，用于电压阻塞和电流传导。 漏极和背面端子能够至少支持器件的额定阻塞电压。 与传统的0001或000-1平面相比，垂直MIS通道可以形成在有利的11-20平面上以实现更高的MIS沟道迁移率，导致与传统垂直方向相比，相同阻断电压导致更低的导通电阻 MOSFET具有相似的阻断电压。

公开(公告)号：US06579775B2

公开(公告)日：2003-06-17

申请号：US10003871

申请日：2001-10-24

申请人： Isik C. Kizilyalli ,  Ranbir Singh ,  Lori Stirling

发明人： Isik C. Kizilyalli ,  Ranbir Singh ,  Lori Stirling

IPC分类号： H01L2120

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L29/4958

摘要： The present invention provides a semiconductor device located on a semiconductor substrate having opposite types of first and second transistors formed thereon. The device preferably includes a first gate electrode that includes a first metal gate electrode material having a work function compatible with the first transistor, and a second gate electrode that includes a second metal gate electrode material having a work function compatible with the second transistor and the first metal gate electrode material is also located over the second metal gate electrode material, which forms a gate stack.

公开(公告)号：US06528845B1

公开(公告)日：2003-03-04

申请号：US09616569

申请日：2000-07-14

申请人： Jeffrey D. Bude ,  Richard J. McPartland ,  Ranbir Singh

发明人： Jeffrey D. Bude ,  Richard J. McPartland ,  Ranbir Singh

IPC分类号： H01L29792

CPC分类号： H01L29/66833 ,  G11C16/0458 ,  G11C16/0466 ,  H01L27/105 ,  H01L27/115 ,  H01L29/7885 ,  H01L29/792

摘要： The present invention provides a semiconductor device that comprises a tub region located in a semiconductor substrate, wherein the tub region has a tub electrical contact connected thereto. The semiconductor device further comprises a trap charge insulator layer located on the first insulator layer and a control gate located over the trap charge insulator layer. The control gate has a gate contact connected thereto for providing a second bias voltage to the semiconductor device that, during programming, is opposite in polarity to that of the first bias voltage.

摘要翻译： 本发明提供了一种半导体器件，其包括位于半导体衬底中的桶区，其中，所述桶区具有与其连接的桶电接触。 半导体器件还包括位于第一绝缘体层上的陷阱电荷绝缘体层和位于阱电荷绝缘体层上方的控制栅极。 控制栅极具有连接到其上的栅极接触，用于向半导体器件提供第二偏置电压，在编程期间极性与第一偏置电压相反。

公开(公告)号：US06459615B1

公开(公告)日：2002-10-01

申请号：US09910980

申请日：2001-07-23

申请人： Richard Joseph McPartland ,  Ranbir Singh

发明人： Richard Joseph McPartland ,  Ranbir Singh

IPC分类号： G11C1604

CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C2216/10 ,  H01L27/11558

摘要： A non-volatile memory device is disclosed which includes an erase device that is shared among an array of memory cells. Each of the memory cells in the array includes a control device coupled to a switch device via a common floating gate. Each of at least a subset of the memory cells further includes a portion of the shared erase device, the portion of the shared erase device associated with a given one of the memory cells being coupled to the switch device of that cell via the floating gate of that cell. The shared erase device is utilizable in performing an erase operation for each of the memory cells associated therewith. Advantageously, the use of the shared erase device substantially reduces the circuit area requirements of the memory array. The invention is particularly well suited for implementation in single-poly flash EEPROM embedded memory devices in integrated circuit applications.

摘要翻译： 公开了一种非易失性存储器件，其包括在存储器单元阵列之间共享的擦除装置。 阵列中的每个存储器单元包括通过公共浮动栅极耦合到开关器件的控制器件。 存储器单元的至少一个子集中的每一个还包括共享擦除装置的一部分，与存储器单元中的给定一个存储器单元相关联的共享擦除装置的部分经由浮动栅极的浮动栅极耦合到该单元的开关装置 那个单元格。 共享擦除装置可用于对与其相关联的每个存储单元执行擦除操作。 有利地，共享擦除装置的使用大大减少了存储器阵列的电路面积要求。 本发明特别适用于集成电路应用中的单聚焦闪存EEPROM嵌入式存储器件中的实现。