公开(公告)号：US20070278539A1

公开(公告)日：2007-12-06

申请号：US11446016

申请日：2006-06-02

申请人： Mark Victor Dyson ,  Nace Rossi ,  Ranbir Singh

发明人： Mark Victor Dyson ,  Nace Rossi ,  Ranbir Singh

IPC分类号： H01L29/76 ,  H01L29/808 ,  H01L21/337

CPC分类号： H01L29/66242 ,  H01L27/0248 ,  H01L29/66901 ,  H01L29/7378 ,  H01L29/808

摘要： A semiconductor device is described that operates as an improved junction field effect transistor (JFET). A bipolar transistor with a collector region, a base region, an emitter region, a first base contact, and a second base contact insulated from the first base contact, has the base region lightly doped to about a 1E16 to 5E17 atoms/cm3 doping level. A connection is provided between the emitter region and the collector region to act as a JFET gate contact for the bipolar transistor. The semiconductor device operates as an improved JFET with the first base contact being a drain contact and the second base contact being a source contact. A method for manufacture of an improved JFET on a chip containing conventional bipolar devices is also described. The improved JFET is shown being used with a write head in a disk drive system for providing electrostatic discharge protection.

摘要翻译： 描述了作为改进的结型场效应晶体管（JFET）工作的半导体器件。 具有集电极区域，基极区域，发射极区域，第一基极触点和与第一基极接触绝缘的第二基极触点的双极晶体管具有轻度掺杂到约1E16至5E17原子/ cm 2的基极区域 > 3 掺杂水平。 在发射极区域和集电极区域之间提供连接以用作双极晶体管的JFET栅极接触。 半导体器件作为改进的JFET工作，第一基极触点是漏极触点，第二基极触点是源极触点。 还描述了用于制造包含常规双极器件的芯片上的改进的JFET的方法。 改进的JFET被示出用于提供静电放电保护的盘驱动系统中的写头。

公开(公告)号：US08685861B2

公开(公告)日：2014-04-01

申请号：US11462036

申请日：2006-08-02

申请人： Chih Ping Yong ,  Peter Chew ,  Chuin Boon Yeap ,  Hoon Lian Yap ,  Ranbir Singh ,  Nace Rossi ,  Jovin Lim

发明人： Chih Ping Yong ,  Peter Chew ,  Chuin Boon Yeap ,  Hoon Lian Yap ,  Ranbir Singh ,  Nace Rossi ,  Jovin Lim

IPC分类号： H01L21/311

CPC分类号： H01L21/76801 ,  H01L21/76804 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A integrated circuit system including providing an integrated circuit device, forming an undoped insulating layer over the integrated circuit device, forming a thin insulating layer over the undoped insulating layer, forming a doped insulating layer over the thin insulating layer, and forming a contact in the undoped insulating layer, thin insulating layer and the doped insulating layer.

摘要翻译： 一种集成电路系统，包括提供集成电路器件，在所述集成电路器件上形成未掺杂绝缘层，在所述未掺杂绝缘层上形成薄绝缘层，在所述薄绝缘层上形成掺杂绝缘层，以及在所述绝缘层上形成接触 未掺杂的绝缘层，薄绝缘层和掺杂绝缘层。

公开(公告)号：US20080014728A1

公开(公告)日：2008-01-17

申请号：US11427494

申请日：2006-06-29

申请人： Nace Rossi ,  Ranbir Singh

发明人： Nace Rossi ,  Ranbir Singh

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L21/76838 ,  H01L21/32051 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention, in one aspect, provides a method of manufacturing a semiconductor device. This method includes providing a semiconductor substrate and depositing a metal layer over the semiconductor substrate that has an overall thickness of about 1 micron or greater. The metal layer is formed by depositing a first portion of the thickness of the metal layer, which has a compressive or tensile stress associated therewith over the semiconductor substrate. A stress-compensating layer is deposited over the first portion, such that the stress-compensating layer imparts a stress to the first portion that is opposite to the compressive or tensile stress associated with the first portion. A second portion of the thickness of the metal layer is then deposited over the stress-compensating layer.

摘要翻译： 本发明在一个方面提供一种制造半导体器件的方法。 该方法包括提供半导体衬底并在半导体衬底上沉积总厚度为约1微米或更大的金属层。 通过在半导体衬底上沉积具有与其相关的压缩或拉伸应力的金属层的厚度的第一部分来形成金属层。 应力补偿层沉积在第一部分上，使得应力补偿层向与第一部分相关联的压缩或拉伸应力相反的第一部分赋予应力。 然后将金属层的厚度的第二部分沉积在应力补偿层上。

公开(公告)号：US20060286739A1

公开(公告)日：2006-12-21

申请号：US11153893

申请日：2005-06-15

申请人： Nace Rossi ,  Ranbir Singh ,  Arun Nanda

发明人： Nace Rossi ,  Ranbir Singh ,  Arun Nanda

IPC分类号： H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： A shallow trench isolation structure having a negative taper angle. A graded doped sacrificial layer is formed over a semiconductor substrate and etched to form a first trench therein having trench sidewalls that present a negative taper angle. The substrate is also etched to form a second trench therein overlying the first trench. Silicon dioxide fills both the first and the second trenches to form the shallow trench isolation structure, with the silicon dioxide in the first trench exhibiting a negative taper angle to avoid formation of polysilicon stringers during a gate polysilicon deposition.

摘要翻译： 具有负锥角的浅沟槽隔离结构。 梯度掺杂牺牲层形成在半导体衬底之上，并被蚀刻以形成其中具有呈负锥度角的沟槽侧壁的第一沟槽。 衬底也被蚀刻以在其中覆盖第一沟槽上形成第二沟槽。 二氧化硅填充第一和第二沟槽两者以形成浅沟槽隔离结构，其中第一沟槽中的二氧化硅呈现负锥角，以避免在栅极多晶硅沉积期间形成多晶硅桁条。

公开(公告)号：US07675179B2

公开(公告)日：2010-03-09

申请号：US11738050

申请日：2007-04-20

申请人： Ranbir Singh ,  Sen Sidhartha ,  Nace Rossi

发明人： Ranbir Singh ,  Sen Sidhartha ,  Nace Rossi

IPC分类号： H01L23/522

CPC分类号： H01L21/02063 ,  H01L21/02052 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76831 ,  Y10S438/963

摘要： The present invention provides an interconnect that can be employed in an integrated circuit. The interconnect includes a metal line located over a substrate, a dielectric layer located over the metal line, and an interconnect located in the dielectric layer, including a landed portion located over the metal line and an unlanded portion located along at least a portion of a lateral edge of the metal line. The unlanded portion is at least partially filled with a polymer, and the landed portion is substantially filled with a conductive material. A method for manufacturing the interconnect is also provided.

摘要翻译： 本发明提供了可以用于集成电路中的互连。 互连包括位于衬底上的金属线，位于金属线上方的电介质层和位于电介质层中的互连，其包括位于金属线上的着陆部分和位于金属线的至少一部分上的非上限部分 金属线的侧边。 至少部分地用聚合物填充未上敷的部分，并且所述着陆部分基本上填充有导电材料。 还提供了用于制造互连的方法。

公开(公告)号：US20080057672A1

公开(公告)日：2008-03-06

申请号：US11926469

申请日：2007-10-29

申请人： Nace Rossi ,  Ranbir Singh ,  Arun Nanda

发明人： Nace Rossi ,  Ranbir Singh ,  Arun Nanda

IPC分类号： H01L21/762

CPC分类号： H01L21/31116 ,  H01L21/76205 ,  H01L21/76232

摘要： A shallow trench isolation structure having a negative taper angle and a method for forming same. A silicon nitride layer formed over a semiconductor substrate is etched according to a plasma etch process to form a first opening therein having sidewalls that present a negative taper angle. The substrate is etched to form a trench therein underlying the first opening. Silicon dioxide fills both the opening and the trench to form the shallow trench isolation structure, with the silicon dioxide in the opening exhibiting a negative taper angle to avoid formation of conductive stringers during subsequent process steps.

摘要翻译： 具有负锥角的浅沟槽隔离结构及其形成方法。 根据等离子体蚀刻工艺蚀刻形成在半导体衬底上的氮化硅层，以形成其中具有负锥角的侧壁的第一开口。 蚀刻衬底以在第一开口下方形成沟槽。 二氧化硅填充开口和沟槽以形成浅沟槽隔离结构，其中开口中的二氧化硅呈现负锥角，以避免在随后的工艺步骤期间形成导电条。

公开(公告)号：US07982286B2

公开(公告)日：2011-07-19

申请号：US11427494

申请日：2006-06-29

申请人： Nace Rossi ,  Ranbir Singh

发明人： Nace Rossi ,  Ranbir Singh

IPC分类号： H01L27/08

CPC分类号： H01L21/76838 ,  H01L21/32051 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention, in one aspect, provides a method of manufacturing a semiconductor device. This method includes providing a semiconductor substrate and depositing a metal layer over the semiconductor substrate that has an overall thickness of about 1 micron or greater. The metal layer is formed by depositing a first portion of the thickness of the metal layer, which has a compressive or tensile stress associated therewith over the semiconductor substrate. A stress-compensating layer is deposited over the first portion, such that the stress-compensating layer imparts a stress to the first portion that is opposite to the compressive or tensile stress associated with the first portion. A second portion of the thickness of the metal layer is then deposited over the stress-compensating layer.

摘要翻译： 本发明在一个方面提供一种制造半导体器件的方法。 该方法包括提供半导体衬底并在半导体衬底上沉积总厚度为约1微米或更大的金属层。 通过在半导体衬底上沉积具有与其相关的压缩或拉伸应力的金属层的厚度的第一部分来形成金属层。 应力补偿层沉积在第一部分上，使得应力补偿层向与第一部分相关联的压缩或拉伸应力相反的第一部分赋予应力。 然后将金属层的厚度的第二部分沉积在应力补偿层上。

公开(公告)号：US07906407B2

公开(公告)日：2011-03-15

申请号：US11926469

申请日：2007-10-29

申请人： Nace Rossi ,  Ranbir Singh ,  Arun K. Nanda

发明人： Nace Rossi ,  Ranbir Singh ,  Arun K. Nanda

IPC分类号： H01L21/76

CPC分类号： H01L21/31116 ,  H01L21/76205 ,  H01L21/76232

摘要： A shallow trench isolation structure having a negative taper angle and a method for forming same. A silicon nitride layer formed over a semiconductor substrate is etched according to a plasma etch process to form a first opening therein having sidewalls that present a negative taper angle. The substrate is etched to form a trench therein underlying the first opening. Silicon dioxide fills both the opening and the trench to form the shallow trench isolation structure, with the silicon dioxide in the opening exhibiting a negative taper angle to avoid formation of conductive stringers during subsequent process steps.

摘要翻译： 具有负锥角的浅沟槽隔离结构及其形成方法。 根据等离子体蚀刻工艺蚀刻形成在半导体衬底上的氮化硅层，以形成其中具有负锥角的侧壁的第一开口。 蚀刻衬底以在第一开口下方形成沟槽。 二氧化硅填充开口和沟槽以形成浅沟槽隔离结构，其中开口中的二氧化硅呈现负锥角，以避免在随后的工艺步骤期间形成导电条。

公开(公告)号：US20090127651A1

公开(公告)日：2009-05-21

申请号：US12356600

申请日：2009-01-21

申请人： Arun K. Nanda ,  Nace Rossi ,  Ranbir Singh

发明人： Arun K. Nanda ,  Nace Rossi ,  Ranbir Singh

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/31116 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/76232

摘要： In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material.

摘要翻译： 在半导体衬底中，具有设置在沟槽填充材料的空隙中的介电材料的浅沟槽隔离结构和用于形成浅沟槽隔离结构的方法。 在电介质材料形成在沟槽中之后，可以在湿式清洁工艺期间形成空隙。 在衬底上和空隙中形成保形氮化硅层。 在移除氮化硅层之后，空隙至少部分地被氮化硅材料填充。

公开(公告)号：US20080029853A1

公开(公告)日：2008-02-07

申请号：US11462036

申请日：2006-08-02

申请人： Chih Ping Yong ,  Peter Chew ,  Chuin Boon Yeap ,  Hoon Lian Yap ,  Ranbir Singh ,  Nace Rossi ,  Jovin Lim

发明人： Chih Ping Yong ,  Peter Chew ,  Chuin Boon Yeap ,  Hoon Lian Yap ,  Ranbir Singh ,  Nace Rossi ,  Jovin Lim

IPC分类号： H01L23/58

CPC分类号： H01L21/76801 ,  H01L21/76804 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A integrated circuit system including providing an integrated circuit device, forming an undoped insulating layer over the integrated circuit device, forming a thin insulating layer over the undoped insulating layer, forming a doped insulating layer over the thin insulating layer, and forming a contact in the undoped insulating layer, thin insulating layer and the doped insulating layer.

摘要翻译： 一种集成电路系统，包括提供集成电路器件，在所述集成电路器件上形成未掺杂绝缘层，在所述未掺杂绝缘层上形成薄绝缘层，在所述薄绝缘层上形成掺杂绝缘层，以及在所述绝缘层上形成接触 未掺杂的绝缘层，薄绝缘层和掺杂绝缘层。