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94 条记录 (耗时 0.04 秒)

    Charging member, process cartridge, and electrophotographic apparatus
    61.
    发明授权
    Charging member, process cartridge, and electrophotographic apparatus 有权
    充电构件，处理盒和电子照相设备

    公开(公告)号：US08064803B2

    公开(公告)日：2011-11-22

    申请号：US12280982

    申请日：2007-02-23

    申请人： Noriaki Kuroda ,  Yoko Kuruma ,  Hisao Kato ,  Toshiro Suzuki ,  Jun Murata

    发明人： Noriaki Kuroda ,  Yoko Kuruma ,  Hisao Kato ,  Toshiro Suzuki ,  Jun Murata

    IPC分类号： G03G15/02

    CPC分类号： G03G15/0233 ,  G03G2215/025 ,  Y10T428/31663

    摘要： A charging member having a support, a conductive elastic layer formed on the support and a surface layer formed on the conductive elastic layer, wherein the surface layer contains a polysiloxane having an acrylic group and an oxyalkylene group. This provides a charging member to the surface of which toners and external additives used in the toners can not easily cling even because of repeated use over a long period of time and which therefore enables charging and image reproduction which are stable over a long period of time, even when used in the DC contact charging method; and further provides a process cartridge and an electrophotographic apparatus which have such a charging member.

    摘要翻译： 具有支撑体的充电构件，形成在支撑体上的导电弹性层和形成在导电弹性层上的表面层，其中表面层含有具有丙烯酸基和氧化烯基的聚硅氧烷。 这提供了一种充电构件，其表面上调色剂中使用的调色剂和外部添加剂即使长时间反复使用也不容易粘附，因此能够长时间稳定的充电和图像再现 ，即使用于直流接触充电方式; 并且还提供具有这种充电部件的处理盒和电子照相设备。

    Device, method, and computer program product for computing electric power consumption
    63.
    发明申请
    Device, method, and computer program product for computing electric power consumption 有权
    用于计算电力消耗的装置，方法和计算机程序产品

    公开(公告)号：US20100235656A1

    公开(公告)日：2010-09-16

    申请号：US12659108

    申请日：2010-02-25

    申请人： Jun Murata

    发明人： Jun Murata

    IPC分类号： G06F1/00

    CPC分类号： G06F1/28 ,  G06F1/3203

    摘要： A disclosed electric power consumption computation device includes an acquisition unit configured to acquire apparatus information from an apparatus connected to the electric power consumption computation device via a predetermined data communication path, and a computation unit configured to compute electric power consumption of the apparatus based on information on a number of output sheets output by the apparatus contained in the apparatus information acquired by the acquisition unit and a TEC value of the apparatus.

    摘要翻译： 所公开的电力消耗计算装置包括：获取单元，被配置为经由预定数据通信路径从连接到所述电力消耗计算装置的装置获取装置信息;以及计算单元，被配置为基于信息计算所述装置的电力消耗 由包含在由获取单元获取的装置信息中的装置输出的多个输出纸张和装置的TEC值。

    COMPOSITE OPTICAL ELEMENT
    65.
    发明申请
    COMPOSITE OPTICAL ELEMENT 有权
    复合光学元件

    公开(公告)号：US20090323502A1

    公开(公告)日：2009-12-31

    申请号：US12304607

    申请日：2007-06-06

    申请人： Jun Murata ,  Toshiaki Takano

    发明人： Jun Murata ,  Toshiaki Takano

    IPC分类号： G11B7/135

    CPC分类号： G02B27/0037 ,  B29D11/00269 ,  B29D11/0073 ,  G02B5/1852 ,  G02B5/1895 ,  G02B27/4238 ,  G02B27/4272 ,  G11B7/1353 ,  G11B7/1374 ,  G11B7/13922 ,  G11B2007/0006

    摘要： The present invention relates to composite optical elements, and particularly to a composite optical element including a first optical component and a second optical component coupled to the first optical component.The present invention is advantageous in enhancing optical properties.A composite optical element (1) includes a first optical component (10) and a second optical component (20). The first optical component (10) is made of first glass and has a lens surface (12). The second optical component (20) is made of a material different from the first glass, is coupled to the first optical component (10) at a lens surface (22), and has a lens surface (22) at a side opposite to the first coupling surface (21). The lens surface (12) partially has a first uneven region (12a). The lens surface (22) partially has a second uneven region (22a).

    摘要翻译： 复合光学元件技术领域本发明涉及复合光学元件，特别涉及包括耦合到第一光学部件的第一光学部件和第二光学部件的复合光学元件。 本发明在增强光学性能方面是有利的。 复合光学元件（1）包括第一光学部件（10）和第二光学部件（20）。 第一光学部件（10）由第一玻璃制成并具有透镜表面（12）。 第二光学部件（20）由与第一玻璃不同的材料制成，在透镜表面（22）处连接到第一光学部件（10），并且在与第一玻璃相对的一侧具有透镜表面（22） 第一联接表面（21）。 透镜表面（12）部分地具有第一凹凸区域（12a）。 透镜表面（22）部分地具有第二凹凸区域（22a）。

    Low stress semiconductor devices with thermal oxide isolation
    68.
    发明授权
    Low stress semiconductor devices with thermal oxide isolation 失效
    具有热氧化隔离的低应力半导体器件

    公开(公告)号：US06310384B1

    公开(公告)日：2001-10-30

    申请号：US08838259

    申请日：1997-04-17

    申请人： Hideo Miura ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

    发明人： Hideo Miura ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

    IPC分类号： H01L2900

    CPC分类号： H01L21/76205 ,  H01L21/76202 ,  H01L27/0802

    摘要： A width of a circuit device isolation region and a width of a device region formed on a semiconductor substrate are determined in such a manner as to satisfy a condition which prevents the occurrence of dislocation due to thermal oxidation for forming the isolation region. In accordance with the manufacturing scheme, a semiconductor device produced includes a semiconductor substrate, a plurality of circuit regions formed on a device formation region in the semiconductor substrate and having a width of 0.1 to 125 &mgr;m and device isolation regions so formed on the semiconductor substrate as to isolate a plurality of circuit regions from one another and having a width of 0.01 to 2.5 &mgr;m. In such a schemed device, a ratio of the width of the device region to the width of the device isolation region is from 2 to 50. Each device isolation region is a groove formed in the semiconductor substrate by etching a portion, among the pad oxide film formed on the surface of the semiconductor substrate and a nitride film formed on the pad oxide film, existing on the device isolation region, and having a depth of from 0 to 10 nm when measured from the position of the pad oxide film on the semiconductor substrate.

    摘要翻译： 确定电路器件隔离区域的宽度和形成在半导体衬底上的器件区域的宽度，以满足防止由于形成隔离区域的热氧化引起的位错发生的条件。 根据制造方案，制造的半导体器件包括半导体衬底，形成在半导体衬底中的器件形成区域上并具有0.1至125μm的宽度的多个电路区域和形成在半导体衬底上的器件隔离区域 以便将多个电路区彼此隔离并且具有0.01至2.5μm的宽度。 在这种设计的器件中，器件区域的宽度与器件隔离区域的宽度的比率为2至50.每个器件隔离区域是通过在衬底氧化物中蚀刻一部分而形成在半导体衬底中的沟槽 形成在半导体衬底的表面上的膜和形成在衬垫氧化膜上的氮化物膜，存在于器件隔离区上，并且当从半导体上的衬垫氧化物膜的位置测量时具有0至10nm的深度 基质。

    Method of producing semiconductor integrated circuit device having switching MISFET and capacitor element including wiring therefor and method of producing such wiring
    69.
    发明授权
    Method of producing semiconductor integrated circuit device having switching MISFET and capacitor element including wiring therefor and method of producing such wiring 失效
    具有开关MISFET和包括其布线的电容器元件的半导体集成电路器件的制造方法以及制造这种布线的方法

    公开(公告)号：US06281071B1

    公开(公告)日：2001-08-28

    申请号：US09317999

    申请日：1999-05-25

    申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

    发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

    IPC分类号： H01L218242

    CPC分类号： H01L27/105 ,  H01L27/10808

    摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. In a fifth aspect, the capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. In sixth and seventh aspects, wiring is provided.

    摘要翻译： 公开了一种具有开关MISFET的半导体集成电路器件和形成在诸如DRAM的半导体衬底之上的电容器元件。 在本发明的第一方面中，电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 在第二方面，Y选择信号线与电容器元件的下电极层重叠。 在第三方面中，通过用于沟道阻挡区域的杂质的扩散，形成至少在电容器元件连接的开关MISFET的半导体区域下方的势垒层。 在第四方面中，电容器元件的电介质膜与其上的电容器电极层共同扩展。 在第五方面中，电容器电介质膜是其上具有氧化硅层的氮化硅膜，通过在高压下氧化氮化硅的表面层而形成氧化硅层。 在第六和第七方面中，提供了布线。