公开(公告)号：US06656752B1

公开(公告)日：2003-12-02

申请号：US09890611

申请日：2001-10-11

申请人： Nobuyuki Mise ,  Tatehito Usui ,  Masato Ikegawa ,  Kazuo Nojiri ,  Kazuyuki Tsunokuni ,  Tetsuo Ono

发明人： Nobuyuki Mise ,  Tatehito Usui ,  Masato Ikegawa ,  Kazuo Nojiri ,  Kazuyuki Tsunokuni ,  Tetsuo Ono

IPC分类号： H01L2166

CPC分类号： H01L22/34

摘要： A wafer is exposed to a plasma. Here, the wafer includes a semiconductor or a conductor 1 provided on an insulator 6, an insulator 2 formed thereon and having a region the thickness of which has been made locally thin, and a 2nd conductor 4 provided on the insulator 2, one of the semiconductor or the conductor 1 and the 2nd conductor 4 having a 1st region from the surface of which a substantially total solid angle is formed, the other having a 2nd region a solid angle formed from the surface of which is made smaller than the 1st region. Then, a voltage is applied to the semiconductor or the conductor 1 and the 2nd conductor 4 so as to measure a time elapsing until the insulator 2 undergoes a dielectric breakdown. Moreover, the ion current density is determined from an electric charge required therefor and an area exposed onto the surface of the 2nd conductor 4. Consequently, it becomes possible to measure, on the wafer, the current density of the ions launched into the wafer, thereby allowing the measuring method of the icon current density to be made suitable for the mass production.

摘要翻译： 将晶片暴露于等离子体。 这里，晶片包括设置在绝缘体6上的半导体或导体1，形成在其上的绝缘体2，其厚度局部变薄的区域和设置在绝缘体2上的第二导体4， 半导体或导体1和第二导体4具有从其表面基本上具有总立体角的第一区域，另一个具有从其表面形成的立体角小于第一区域的第二区域。 然后，向半导体或导体1和第二导体4施加电压，以测量直到绝缘体2经历介电击穿的时间。 此外，离子电流密度由其所需的电荷和暴露于第二导体4的表面的面积确定。因此，可以在晶片上测量发射到晶片中的离子的电流密度， 从而允许图标电流密度的测量方法适合于批量生产。

公开(公告)号：US06340632B1

公开(公告)日：2002-01-22

申请号：US09585629

申请日：2000-06-02

申请人： Shinichi Fukada ,  Kazuo Nojiri ,  Takashi Yunogami ,  Shoji Hotta ,  Hideo Aoki ,  Takayuki Oshima ,  Nobuyoshi Kobayashi

发明人： Shinichi Fukada ,  Kazuo Nojiri ,  Takashi Yunogami ,  Shoji Hotta ,  Hideo Aoki ,  Takayuki Oshima ,  Nobuyoshi Kobayashi

IPC分类号： H01L214763

CPC分类号： H01L21/76874 ,  H01L21/76804 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.

摘要翻译： 绝缘膜34至38（其绝缘膜34,36,38是氮化硅膜和绝缘膜35,38是氧化硅膜）依次形成在第四布线层的布线33上，并将凹槽图案40转移到 绝缘膜38。 形成防反射膜41以填充绝缘膜38的槽40，然后形成承载孔图案43的抗蚀剂膜42。 在存在抗蚀剂膜42的情况下对膜进行蚀刻操作，以将孔图案转印到绝缘膜38,37,36和绝缘膜35的一部分中。随后，将抗蚀剂膜42和抗反射膜 41，并且通过使用绝缘膜38作为掩模将槽图案40和孔图案43分别转印到绝缘膜37和绝缘膜35中。

公开(公告)号：US6077788A

公开(公告)日：2000-06-20

申请号：US469998

申请日：1995-06-06

申请人： Yoshinao Kawasaki ,  Hironobu Kawahara ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Kazuo Nojiri ,  Yoshimi Torii

发明人： Yoshinao Kawasaki ,  Hironobu Kawahara ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Kazuo Nojiri ,  Yoshimi Torii

IPC分类号： C23F4/00 ,  H01L21/00 ,  H01L21/677 ,  H01L21/302 ,  C23F1/02

CPC分类号： H01L21/67161 ,  C23F4/00 ,  H01L21/67028 ,  H01L21/67745 ,  H01L21/67751

摘要： Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus, the samples being selectively etched through use of a resist mask), (b) for removing (ashing) the resist mask, (c) for wet-processing of the samples and (d) for dry-processing the samples. Samples are passed sequentially from a supply cassette (containing a plurality of samples) to the plasma etching apparatus, through the other apparatus and to a discharge cassette (which can hold a plurality of the samples). At least two of the samples can be processed simultaneously in a path from (and including), the plasma etching apparatus to (and including) the wet-processing structure.

摘要翻译： 公开了用于处理样品的装置以及使用该装置的方法。 该装置包括用于处理样品的处理装置（例如，等离子体蚀刻装置，通过使用抗蚀剂掩模选择性地蚀刻样品），（b）去除（灰化）抗蚀剂掩模，（c） 处理样品和（d）干燥处理样品。 样品从供应盒（含有多个样品）顺序地通过另一个装置和放电盒（可以容纳多个样品）通过等离子体蚀刻装置。 至少两个样品可以在等离子体蚀刻装置（并且包括）湿法处理结构的路径中（并且包括）的同时进行处理。

公开(公告)号：US5917211A

公开(公告)日：1999-06-29

申请号：US979543

申请日：1997-11-25

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

IPC分类号： H01L21/8234 ,  H01L27/105 ,  H01L27/08 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/105 ,  H01L21/823425

摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.

摘要翻译： 一种半导体集成电路，包括构成存储系统的存储单元的第一n沟道MISFET，构成存储系统的外围电路的第二n沟道MISFET和构成外围电路中的输出电路的第三n沟道MISFET。 当这些MISFET的各个栅极长度基本相同时，第一n沟道MISFET，第二n沟道MISFET和第三n沟道MISFET的阈值电压依次减小。

公开(公告)号：US5568277A

公开(公告)日：1996-10-22

申请号：US464556

申请日：1995-06-06

申请人： Yasuhiro Hatano ,  Hajime Takayama ,  Yasushi Fukada ,  Kazuhiko Kurita ,  Kazuo Nojiri

发明人： Yasuhiro Hatano ,  Hajime Takayama ,  Yasushi Fukada ,  Kazuhiko Kurita ,  Kazuo Nojiri

IPC分类号： H04N1/00 ,  H04N1/12 ,  H04N1/193 ,  H04N1/04 ,  H04N1/191

CPC分类号： H04N1/00525 ,  H04N1/121 ,  H04N1/00885 ,  H04N1/193

摘要： The facsimile apparatus includes a casing with a handset arranged on a side thereof. Within the casing are disposed a network control section adjacent the handset and a power supply section opposite the network control section. A control board is arranged above the network control and power supply sections. The control board includes an analog signal control section adjacent to the network control section, a driving control section adjacent to the power supply section for driving a preselected electrical part, and a digital signal control section between the analog signal control section and the driving control section.

摘要翻译： 该传真装置包括一个设置在其一侧的手机壳体。 在壳体内设置有与手机相邻的网络控制部分和与网络控制部分相对的电源部分。 控制板设置在网络控制和电源部分上方。 控制板包括与网络控制部分相邻的模拟信号控制部分，与电源部分相邻的用于驱动预选电气部分的驱动控制部分，以及模拟信号控制部分和驱动控制部分之间的数字信号控制部分 。

公开(公告)号：US5433789A

公开(公告)日：1995-07-18

申请号：US010051

申请日：1993-01-28

申请人： Yutaka Kakehi ,  Yoshinao Kawasaki ,  Keizo Suzuki ,  Kazuo Nojiri ,  Hiromichi Enami ,  Tetsunori Kaji ,  Seiichi Watanabe ,  Yoshifumi Ogawa

发明人： Yutaka Kakehi ,  Yoshinao Kawasaki ,  Keizo Suzuki ,  Kazuo Nojiri ,  Hiromichi Enami ,  Tetsunori Kaji ,  Seiichi Watanabe ,  Yoshifumi Ogawa

IPC分类号： C23C16/511 ,  H01J37/32 ,  C23C16/30 ,  H05H1/46

CPC分类号： H01J37/32229 ,  C23C16/511 ,  H01J37/32192 ,  H01J37/32266 ,  H01J37/32284

摘要： A plasma processing apparatus has a waveguide along which microwaves are propagated from a microwave generator to a plasma-forming region in a low-pressure processing chamber. The waveguide has a large cross-sectional area, to enable a large region of plasma to be achieved. Uniformity and stability of the plasma are improved by a mode restrictor which inhibits mixing of propagation modes which is otherwise liable to occur in a wide waveguide. The mode restrictor consists of electrically-conductive dividers which divide the waveguide cross-section into an array of sub-guides before the plasma-forming region.

摘要翻译： 等离子体处理装置具有微波从微波发生器传播到低压处理室中的等离子体形成区域的波导。 波导具有大的横截面面积，以实现等离子体的大区域。 等离子体的均匀性和稳定性通过抑制混合传播模式的模式限制器来改善，否则传播模式容易发生在宽波导中。 模式限制器由导电分配器组成，其在等离子体形成区域之前将波导横截面分成子导轨阵列。

公开(公告)号：US07132293B2

公开(公告)日：2006-11-07

申请号：US10854155

申请日：2004-05-27

申请人： Yoshimi Torii ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

发明人： Yoshimi Torii ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

IPC分类号： G01N35/00

CPC分类号： H01L21/67069 ,  H01L21/02071 ,  H01L21/31138 ,  H01L21/67028 ,  H01L21/67173 ,  H01L21/67745 ,  Y10S438/963 ,  Y10T436/11 ,  Y10T436/25 ,  Y10T436/2575

摘要： Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

公开(公告)号：US06607988B2

公开(公告)日：2003-08-19

申请号：US09749554

申请日：2000-12-28

申请人： Takashi Yunogami ,  Yoshitaka Nakamura ,  Kazuo Nojiri ,  Sukeyoshi Tsunekawa ,  Toshiyuki Arai ,  Miwako Nakahara ,  Shigeru Ohno ,  Tomonori Saeki ,  Masaru Izawa

发明人： Takashi Yunogami ,  Yoshitaka Nakamura ,  Kazuo Nojiri ,  Sukeyoshi Tsunekawa ,  Toshiyuki Arai ,  Miwako Nakahara ,  Shigeru Ohno ,  Tomonori Saeki ,  Masaru Izawa

IPC分类号： H01L21302

CPC分类号： H01L28/65 ,  C23F4/00 ,  H01L21/32136 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/91

摘要： With a view to providing a technique for highly-selective etching of Ru (ruthenium) using a photoresist as an etching mask, an Ru-film, which is an lower electrode material deposited on the side walls and bottom surface of a hole, is covered with a photoresist film, followed by isotropic dry etching in a gas atmosphere containing an ozone gas, whereby a portion of the Ru film outside of the hole is removed.

摘要翻译： 为了提供使用光致抗蚀剂作为蚀刻掩模对Ru（钌）进行高选择性蚀刻的技术，覆盖沉积在孔的侧壁和底表面上的下电极材料的Ru膜被覆盖 与光致抗蚀剂膜接触，然后在含有臭氧气体的气体气氛中进行各向同性的干法蚀刻，由此除去孔外部的Ru膜的一部分。

公开(公告)号：US06537417B2

公开(公告)日：2003-03-25

申请号：US09985308

申请日：2001-11-02

申请人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

发明人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

IPC分类号： H01L213065

CPC分类号： H01L21/32136 ,  C23F4/00 ,  H01J37/185 ,  H01L21/67017 ,  H01L21/67028 ,  H01L21/67069 ,  H01L21/67161 ,  H01L21/67207 ,  H01L21/67745 ,  H01L21/67751

摘要： Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

公开(公告)号：US06326218B1

公开(公告)日：2001-12-04

申请号：US09575442

申请日：2000-05-22

申请人： Takashi Yunogami ,  Kazuo Nojiri ,  Yuzuru Ohji ,  Sukeyoshi Tsunekawa ,  Masahiko Hiratani ,  Yuichi Matsui

发明人： Takashi Yunogami ,  Kazuo Nojiri ,  Yuzuru Ohji ,  Sukeyoshi Tsunekawa ,  Masahiko Hiratani ,  Yuichi Matsui

IPC分类号： H01G706

CPC分类号： H01L27/105 ,  H01L21/32139 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L28/60

摘要： Described is a manufacturing method of an integrated circuit which uses a thin film such as platinum or BST as a hard mask upon patterning ruthenium or the like, thereby making it possible to form a device without removing the hard mask. In addition, the invention method makes it possible to interpose a protecting film such as platinum in order to prevent, upon removing a resist used for the patterning of the hard mask, an underlying ruthenium film or the like from being damaged.

摘要翻译： 描述了在图案化钌等上使用诸如铂或BST之类的薄膜作为硬掩模的集成电路的制造方法，从而可以在不去除硬掩模的情况下形成器件。 另外，本发明的方法可以插入诸如铂的保护膜，以便在去除用于图案化硬掩模的抗蚀剂时，下面的钌膜等被损坏。