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    Method of producing semiconductor integrated circuit device having switching MISFET and capacitor element including wiring therefor and method of producing such wiring
    4.
    发明授权
    Method of producing semiconductor integrated circuit device having switching MISFET and capacitor element including wiring therefor and method of producing such wiring 失效
    具有开关MISFET和包括其布线的电容器元件的半导体集成电路器件的制造方法以及制造这种布线的方法

    公开(公告)号：US06281071B1

    公开(公告)日：2001-08-28

    申请号：US09317999

    申请日：1999-05-25

    申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

    发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

    IPC分类号： H01L218242

    CPC分类号： H01L27/105 ,  H01L27/10808

    摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. In a fifth aspect, the capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. In sixth and seventh aspects, wiring is provided.

    摘要翻译： 公开了一种具有开关MISFET的半导体集成电路器件和形成在诸如DRAM的半导体衬底之上的电容器元件。 在本发明的第一方面中，电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 在第二方面，Y选择信号线与电容器元件的下电极层重叠。 在第三方面中，通过用于沟道阻挡区域的杂质的扩散，形成至少在电容器元件连接的开关MISFET的半导体区域下方的势垒层。 在第四方面中，电容器元件的电介质膜与其上的电容器电极层共同扩展。 在第五方面中，电容器电介质膜是其上具有氧化硅层的氮化硅膜，通过在高压下氧化氮化硅的表面层而形成氧化硅层。 在第六和第七方面中，提供了布线。

    Semiconductor integrated circuit device having switching MISFET and capacitor element and method of producing the same, including wiring therefor and method of producing such wiring
    5.
    发明授权
    Semiconductor integrated circuit device having switching MISFET and capacitor element and method of producing the same, including wiring therefor and method of producing such wiring 失效
    具有开关MISFET和电容器元件的半导体集成电路器件及其制造方法，包括其布线及其制造方法

    公开(公告)号：US5753550A

    公开(公告)日：1998-05-19

    申请号：US620867

    申请日：1996-03-25

    申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

    发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

    CPC分类号： H01L27/105 ,  H01L27/10808

    摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In other aspects, a Y-select signal line overlaps the lower electrode layer of the capacitor element; a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region; the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it, the capacitor dielectric film being a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure; an aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide, is used as the protective layer for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.

    摘要翻译： 公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。 在第一方面中，电容器元件所连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 在其他方面，Y选择信号线与电容器元件的下电极层重叠; 至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成; 电容器元件的电介质膜与其上的电容器电极层共同扩展，电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过氧化氮化硅的表面层而形成 在高压下 通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物用作用于包含添加元素（例如Cu）以防止迁移的铝布线的保护层。

    Method of producing semiconductor integrated circuit device having switching MISFET and capacitor element including wiring
    6.
    发明授权
    Method of producing semiconductor integrated circuit device having switching MISFET and capacitor element including wiring 失效
    具有开关MISFET和包括布线的电容元件的半导体集成电路器件的制造方法

    公开(公告)号：US5930624A

    公开(公告)日：1999-07-27

    申请号：US13605

    申请日：1998-01-26

    申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

    发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

    CPC分类号： H01L27/105 ,  H01L27/10808

    摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In other aspects, a Y-select signal line overlaps the lower electrode layer of the capacitor element; a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region; the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it, the capacitor dielectric film being a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure; an aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide, is used as the protective layer for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.

    摘要翻译： 公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。 在第一方面中，电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 在其他方面，Y选择信号线与电容器元件的下电极层重叠; 至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成; 电容器元件的电介质膜与其上的电容器电极层共同扩展，电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过氧化氮化硅的表面层而形成 在高压下 通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物用作用于包含添加元素（例如Cu）以防止迁移的铝布线的保护层。

    Semiconductor integrated circuit device having switching MISFET and capacitor element and method of producing the same, including wiring therefor and method of producing such wiring
    8.
    发明授权
    Semiconductor integrated circuit device having switching MISFET and capacitor element and method of producing the same, including wiring therefor and method of producing such wiring 失效
    具有开关MISFET和电容器元件的半导体集成电路器件及其制造方法，包括其布线及其制造方法

    公开(公告)号：US5153685A

    公开(公告)日：1992-10-06

    申请号：US246514

    申请日：1988-09-19

    申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

    发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

    CPC分类号： H01L27/105 ,  H01L27/10808

    摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. In a fifth aspect, the capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. In sixth and seventh aspects, wiring is provided. In the sixth aspect, an aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; in the seventh aspect, a refractory metal, or a refractory metal silicide QSI.sub.x, where Q is a refractory metal and 0

    摘要翻译： 公开了一种具有开关MISFET的半导体集成电路器件和形成在诸如DRAM的半导体衬底之上的电容器元件。 在本发明的第一方面中，电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 在第二方面，Y选择信号线与电容器元件的下电极层重叠。 在第三方面中，通过用于沟道阻挡区域的杂质的扩散，形成至少在电容器元件连接的开关MISFET的半导体区域下方的势垒层。 在第四方面中，电容器元件的电介质膜与其上的电容器电极层共同扩展。 在第五方面中，电容器电介质膜是其上具有氧化硅层的氮化硅膜，通过在高压下氧化氮化硅的表面层而形成氧化硅层。 在第六和第七方面中，提供了布线。 在第六方面中，在相同的真空溅射室中通过溅射形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 在第七方面中，将含有添加元素（例如Cu）的铝配线用作难熔金属或难熔金属硅化物QSIx（其中Q为难熔金属且0

    Method of producing semiconductor integrated circuit device having memory cell and peripheral circuit MISFETs
    9.
    发明授权
    Method of producing semiconductor integrated circuit device having memory cell and peripheral circuit MISFETs 失效
    具有存储单元和外围电路MISFET的半导体集成电路器件的制造方法

    公开(公告)号：US5504029A

    公开(公告)日：1996-04-02

    申请号：US254562

    申请日：1994-06-06

    申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

    发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/105 ,  H01L27/10808

    摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. The impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. The Y-select signal line overlaps the lower electrode layer of the capacitor element. A potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. The dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. The capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. An aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide QSi.sub.x, where Q is a refractory metal and x is between 0 and 2, is used as a protective layer, for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.

    摘要翻译： 公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。 电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 Y选择信号线与电容器元件的下电极层重叠。 至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成。 电容器元件的电介质膜与其上的电容器电极层共同扩展。 电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过在高压下氧化氮化硅的表面层而形成。 通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物QSix，其中Q是难熔金属，x在0和2之间，用作含有添加元素（例如Cu）以防止迁移的铝布线的保护层。

    Semiconductor integrated circuit device including memory cells having a structure effective in suppression of leak current
    10.
    发明授权
    Semiconductor integrated circuit device including memory cells having a structure effective in suppression of leak current 失效
    包括具有抑制漏电流的结构的存储单元的半导体集成电路器件

    公开(公告)号：US5349218A

    公开(公告)日：1994-09-20

    申请号：US875653

    申请日：1992-04-29

    申请人： Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Toru Kaga ,  Jun Murata ,  Osaomi Enomoto

    发明人： Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Toru Kaga ,  Jun Murata ,  Osaomi Enomoto

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

    CPC分类号： H01L27/10829

    摘要： A semiconductor integrated circuit device has a semiconductor memory cell array including word lines, data lines and a plurality of memory cells provided at cross points of the word and data lines. Each memory cell has a cell selection transistor and an information storage capacitor connected in series. The cell selection transistor in one cell includes first and second doped regions formed in a main surface of a semiconductor substrate, a first insulating film formed on the main surface between the first and second doped regions and a control electrode layer formed on the first insulating film between the first and second doped regions. The first doped region is connected with a data line, while the control electrode is connected with a word line. The information storage capacitor includes a second insulating film formed on the wall of one trench formed on the main surface of the substrate, an electrode layer formed on the second insulating film and serving as a first electrode of the capacitor, a dielectric film formed on the electrode layer and a conducting material provided to fill a space defined by the dielectric film in the trench and serving as a second electrode of the capacitor. The second doped region of the transistor terminates at the wall of the trench. A conducting layer is provided to extend both on the second doped region and the conducting material in the cell to electrically interconnect them for the series connection.

    摘要翻译： 半导体集成电路器件具有半导体存储单元阵列，该半导体存储单元阵列包括在字和数据线的交叉点处设置的字线，数据线和多个存储单元。 每个存储单元具有串联连接的单元选择晶体管和信息存储电容器。 一个单元中的单元选择晶体管包括形成在半导体衬底的主表面中的第一和第二掺杂区，形成在第一和第二掺杂区之间的主表面上的第一绝缘膜和形成在第一绝缘膜上的控制电极层 在第一和第二掺杂区域之间。 第一掺杂区域与数据线连接，而控制电极与字线连接。 信息存储电容器包括形成在形成在基板的主表面上的一个沟槽的壁上的第二绝缘膜，形成在第二绝缘膜上并用作电容器的第一电极的电极层，形成在第二绝缘膜上的电介质膜 电极层和设置成填充由沟槽中的电介质膜限定的空间并用作电容器的第二电极的导电材料。 晶体管的第二掺杂区域终止于沟槽的壁。 提供导电层以在第二掺杂区域和电池中的导电材料两者上延伸以将它们互连用于串联连接。