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    Method of designing a semiconductor device
    1.
    发明授权
    Method of designing a semiconductor device 失效
    设计半导体器件的方法

    公开(公告)号：US06949387B2

    公开(公告)日：2005-09-27

    申请号：US10626718

    申请日：2003-07-25

    申请人： Hideo Miura ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

    发明人： Hideo Miura ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

    IPC分类号： H01L21/762 ,  H01L27/08 ,  H01L21/66

    CPC分类号： H01L21/76205 ,  H01L21/76202 ,  H01L27/0802

    摘要： A technique for a semiconductor device is provided that includes forming circuit regions on a device formation region and device isolation regions on a semiconductor substrate, a ratio of the width of a device isolation region to the width of adjacent circuit regions thereto is set at 2 to 50. A design method is also provided and includes conducting measurements such as of thicknesses of a pad oxide film and a nitride film, the internal stress of the nitride film, the width of both device formation and isolation regions, the depth of the etched portion of the nitride film for forming the groove in a device isolation region, conducting stress analysis in the proximity of the groove due to thermal oxidation, and setting values pertaining to the width of the device formation region and of the device isolation region which do not lead to occurrence of dislocation.

    摘要翻译： 提供了一种半导体器件的技术，其包括在器件形成区域上形成电路区域和半导体衬底上的器件隔离区域，器件隔离区域的宽度与其相邻电路区域的宽度的比率被设置为2至 还提供了一种设计方法，包括进行测量，例如衬垫氧化膜和氮化物膜的厚度，氮化物膜的内部应力，器件形成和隔离区域的宽度，蚀刻部分的深度 的用于在器件隔离区域中形成沟槽的氮化物膜，由于热氧化而在沟槽附近进行导电应力分析，以及与器件形成区域的宽度和不引导的器件隔离区域的设定值 发生脱位。

    Semiconductor device having circuit element in stress gradient region by film for isolation and method of manufacturing the same
    2.
    发明授权
    Semiconductor device having circuit element in stress gradient region by film for isolation and method of manufacturing the same 失效
    具有用于隔离膜的应力梯度区域中的电路元件的半导体器件及其制造方法

    公开(公告)号：US5889312A

    公开(公告)日：1999-03-30

    申请号：US890997

    申请日：1997-07-10

    申请人： Hideo Miura ,  Yasunobu Tanizaki ,  Eiji Wakimoto ,  Shinji Sakata ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

    发明人： Hideo Miura ,  Yasunobu Tanizaki ,  Eiji Wakimoto ,  Shinji Sakata ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

    IPC分类号： H01L21/762 ,  H01L27/08 ,  H01L3/22 ,  H01L21/265

    CPC分类号： H01L21/76202 ,  H01L27/0802

    摘要： A semiconductor device includes a thermal oxide film for isolation, a semiconductor region that becomes an element forming region with the circumference thereof surrounded by the oxide film and diffused resistance layers in the semiconductor region and provides a structure for controlling resistance value variation of diffused resistors originated in a stress generated at time of forming the oxide film for isolation. A distance between an end portion on a longer side closest to a thermal oxide film of the diffused layer and an end of the thermal oxide film is apart from each other by a predetermined value determined by stress distribution in the semiconductor region or by at least 4 .mu.m or more, the longitudinal direction of the diffused layer portion formed from the end of the thermal oxide film over to a stress distribution (gradient) forming region in the semiconductor region is parallel to the forming direction of the stress gradient, and resistance value distribution is formed parallel to the stress gradient in the diffused layer formed from the end of the thermal oxide film over to the stress distribution forming region in the semiconductor region.

    摘要翻译： 半导体器件包括用于隔离的热氧化膜，半导体区域，其成为元件形成区域，其周边被半导体区域中的氧化物膜和扩散电阻层包围，并且提供用于控制起始的扩散电阻器的电阻值变化的结构 在形成用于隔离的氧化膜时产生的应力。 最靠近扩散层的热氧化膜的较长侧的端部与热氧化膜的端部之间的距离彼此分开由半导体区域中的应力分布确定的预定值或至少4 从热氧化膜的端部到半导体区域的应力分布（梯度）形成区域形成的扩散层部的纵向方向平行于应力梯度的形成方向，电阻值 分布形成为平行于从热氧化膜的端部到半导体区域中的应力分布形成区域形成的扩散层中的应力梯度。

    Low stress semiconductor devices with thermal oxide isolation
    3.
    发明授权
    Low stress semiconductor devices with thermal oxide isolation 失效
    具有热氧化隔离的低应力半导体器件

    公开(公告)号：US06310384B1

    公开(公告)日：2001-10-30

    申请号：US08838259

    申请日：1997-04-17

    申请人： Hideo Miura ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

    发明人： Hideo Miura ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

    IPC分类号： H01L2900

    CPC分类号： H01L21/76205 ,  H01L21/76202 ,  H01L27/0802

    摘要： A width of a circuit device isolation region and a width of a device region formed on a semiconductor substrate are determined in such a manner as to satisfy a condition which prevents the occurrence of dislocation due to thermal oxidation for forming the isolation region. In accordance with the manufacturing scheme, a semiconductor device produced includes a semiconductor substrate, a plurality of circuit regions formed on a device formation region in the semiconductor substrate and having a width of 0.1 to 125 &mgr;m and device isolation regions so formed on the semiconductor substrate as to isolate a plurality of circuit regions from one another and having a width of 0.01 to 2.5 &mgr;m. In such a schemed device, a ratio of the width of the device region to the width of the device isolation region is from 2 to 50. Each device isolation region is a groove formed in the semiconductor substrate by etching a portion, among the pad oxide film formed on the surface of the semiconductor substrate and a nitride film formed on the pad oxide film, existing on the device isolation region, and having a depth of from 0 to 10 nm when measured from the position of the pad oxide film on the semiconductor substrate.

    摘要翻译： 确定电路器件隔离区域的宽度和形成在半导体衬底上的器件区域的宽度，以满足防止由于形成隔离区域的热氧化引起的位错发生的条件。 根据制造方案，制造的半导体器件包括半导体衬底，形成在半导体衬底中的器件形成区域上并具有0.1至125μm的宽度的多个电路区域和形成在半导体衬底上的器件隔离区域 以便将多个电路区彼此隔离并且具有0.01至2.5μm的宽度。 在这种设计的器件中，器件区域的宽度与器件隔离区域的宽度的比率为2至50.每个器件隔离区域是通过在衬底氧化物中蚀刻一部分而形成在半导体衬底中的沟槽 形成在半导体衬底的表面上的膜和形成在衬垫氧化膜上的氮化物膜，存在于器件隔离区上，并且当从半导体上的衬垫氧化物膜的位置测量时具有0至10nm的深度 基质。

    Method of fabricating low stress semiconductor devices with thermal oxide isolation
    4.
    发明授权
    Method of fabricating low stress semiconductor devices with thermal oxide isolation 失效
    制造具有热氧化隔离的低应力半导体器件的方法

    公开(公告)号：US06620704B2

    公开(公告)日：2003-09-16

    申请号：US09893980

    申请日：2001-06-29

    申请人： Hideo Miura ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

    发明人： Hideo Miura ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

    IPC分类号： H01L2176

    CPC分类号： H01L21/76205 ,  H01L21/76202 ,  H01L27/0802

    摘要： A method is provided of fabricating a semiconductor device that includes forming a silicon oxide film on a semiconductor substrate. A silicon nitrite film may be formed on the silicon oxide film. A portion of the silicon nitrite film and the silicon oxide film may be removed at a desired portion. Additionally, a groove may be formed in the semiconductor substrate in the portion in which the silicon oxide film is removed. A part of the silicon oxide film may be etched back around the groove with hydrofluoric acid type at the portion in which the silicon nitrite film is located above. Additionally, an oxidized film may be formed in the groove of the semiconductor substrate and the groove may be oxidized.

    摘要翻译： 提供一种制造半导体器件的方法，该半导体器件包括在半导体衬底上形成氧化硅膜。 可以在氧化硅膜上形成亚硝酸硅膜。 可以在期望的部分去除一部分亚硝酸硅膜和氧化硅膜。 此外，可以在除去氧化硅膜的部分中的半导体衬底中形成沟槽。 氧化硅膜的一部分可以在硅亚硝酸盐膜位于上方的部分用氢氟酸型蚀刻回到槽周围。 此外，可以在半导体衬底的沟槽中形成氧化膜，并且可以使沟槽被氧化。

    Semiconductor memory
    8.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US5119332A

    公开(公告)日：1992-06-02

    申请号：US515345

    申请日：1990-04-30

    申请人： Katsuhiro Shimohigashi ,  Hiroo Masuda ,  Hiroshi Kawamoto

    发明人： Katsuhiro Shimohigashi ,  Hiroo Masuda ,  Hiroshi Kawamoto

    IPC分类号： G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  H01L23/522 ,  H01L27/108

    CPC分类号： H01L27/108 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  H01L23/522 ,  H01L27/10805 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed to a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

    摘要翻译： 单元存储单元型的动态RAM集成电路设置有多条数据线，读出放大器，以与数据线相交的方式设置的多条字线，以及设置在数据线上的存储单元 数据线与字线之间的交点。 RAM包括P型半导体衬底和形成在衬底中的N型阱区。 存储单元设置在阱内，并且连接到日期线的读出放大器被构造成形成在半导体衬底中的一对N沟道MOSFET和形成在阱区中的一对P沟道MOSFET 。