公开(公告)号：US4086611A

公开(公告)日：1978-04-25

申请号：US733930

申请日：1976-10-19

申请人： Jun-ichi Nishizawa ,  Kentaro Nakamura ,  Takashi Kitsuregawa

发明人： Jun-ichi Nishizawa ,  Kentaro Nakamura ,  Takashi Kitsuregawa

IPC分类号： H01L29/739 ,  H01L29/74

CPC分类号： H01L29/7392 ,  Y10S148/088

摘要： The disclosed thyristor comprises an n.sup.- semi-conductor layer, a p.sup.- semiconductor layer disposed on one surface of the n.sup.- layer to form a pn junction between them, an n.sup.+ and a p.sup.+ semiconductor layer disposed on the other surfaces of the n.sup.- and p.sup.- layers respectively to serve as main electrodes and a p.sup.+ and a n.sup.+ apertured gate layers disposed within the n.sup.- and p.sup.- layers respectively and provided with a gate electrode. An intrinsic semiconductor layer may be substituted for the n.sup.- and p.sup.- layers. A process of producing such a thyristor is also disclosed.

摘要翻译： 公开的晶闸管包括n型半导体层，p-半导体层，其设置在n层的一个表面上以在它们之间形成pn结，n +和p +半导体层设置在n- 和p层分别用作主电极和分别设置在n层和p层内的p +和n +孔栅层，并设置有栅电极。 本征半导体层可以代替n层和p层。 还公开了制造这种晶闸管的工艺。

公开(公告)号：US5532511A

公开(公告)日：1996-07-02

申请号：US409684

申请日：1995-03-23

申请人： Jun-ichi Nishizawa ,  Toru Kurabayashi

发明人： Jun-ichi Nishizawa ,  Toru Kurabayashi

IPC分类号： H01L21/285 ,  H01L21/335 ,  H01L29/772 ,  H01L29/80 ,  H01L29/04 ,  H01L31/036 ,  H01L31/112

CPC分类号： H01L29/66454 ,  H01L21/28587 ,  H01L29/7722 ,  H01L29/802

摘要： A semiconductor device includes a substrate crystal of a type for epitaxial growth thereon. The substrate crystal has a (111)A face and a (111)B face. Also provided are at least two semiconductor regions of different conductivity types deposited by way of epitaxial growth on the (111)A face of the substrate crystal according to metal organic chemical vapor deposition, thereby providing a structure having a source and a drain. A gate side includes the (111)B face of the substrate crystal. A gate insulating layer is deposited by way of epitaxial growth on the gate side according to molecular layer epitaxy. Alternatively, the at least two semiconductor regions may be deposited on the (111)B face of the substrate crystal according to molecular layer epitaxy, and the gate insulating layer may be deposited on the (111)A face of the substrate crystal according to metal organic chemical vapor deposition.

摘要翻译： 半导体器件包括其上用于外延生长的类型的衬底晶体。 衬底晶体具有（111）A面和（111）B面。 还提供了根据金属有机化学气相沉积在衬底晶体的（111）A面上通过外延生长沉积的不同导电类型的至少两个半导体区域，由此提供具有源极和漏极的结构。 栅极侧包括衬底晶体的（111）B面。 根据分子层外延，栅极绝缘层通过外延生长沉积在栅极侧。 或者，可以根据分子层外延将至少两个半导体区域沉积在衬底晶体的（111）B面上，并且栅极绝缘层可以根据金属沉积在衬底晶体的（111）A面上 有机化学气相沉积。

公开(公告)号：US5500079A

公开(公告)日：1996-03-19

申请号：US237417

申请日：1994-05-03

申请人： Jun-ichi Nishizawa ,  Kenji Yamamoto

发明人： Jun-ichi Nishizawa ,  Kenji Yamamoto

IPC分类号： H01L21/302 ,  H01L21/203 ,  H01L21/268 ,  H01L21/306 ,  H01L21/00

CPC分类号： H01L21/30621 ,  H01L21/2686

摘要： A semiconductor material to be etched is held in a reaction chamber at a predetermined temperature. A reactive etching gas such as a chlorine gas is introduced into the reaction chamber for a first period of time. Thereafter, the reaction chamber is evacuated for a second period of time, and ultraviolet radiation is applied to the semiconductor material for a third period of time within the second period of time for thereby etching the semiconductor material to a depth on the order of a molecular or atomic layer.

摘要翻译： 将要蚀刻的半导体材料在预定温度下保持在反应室中。 反应性蚀刻气体如氯气在反应室中被引入第一段时间。 此后，将反应室抽真空第二时间，并且在第二时间段内对半导体材料施加紫外线辐射第三时间，从而将半导体材料蚀刻到分子量级的深度 或原子层。

公开(公告)号：US5485017A

公开(公告)日：1996-01-16

申请号：US241447

申请日：1994-05-11

申请人： Jun-ichi Nishizawa

发明人： Jun-ichi Nishizawa

IPC分类号： H01L21/329 ,  H01L29/739 ,  H01L29/861 ,  H01L29/06 ,  H01L21/265

CPC分类号： H01L29/66356 ,  H01L29/66196 ,  H01L29/739 ,  H01L29/8616

摘要： A semiconductor device has an n.sup.+ source region, a first n.sup.- channel region, a barrier layer, a second n.sup.- channel region, a pair of n.sup.+ drain regions, an insulating film, and a pair of metal electrodes over the respective n.sup.+ drain regions, all successively disposed on an upper surface of an n.sup.+ crystal substrate. The drain regions and the metal electrodes jointly provide a storage electric capacitance. A source electrode is disposed on the lower surface of the n.sup.+ crystal substrate. Bit information can be written and read at a high speed by tunneling through the barrier layer. According to a method of manufacturing the above semiconductor device, the n.sup.+ source region, the first n.sup.- channel region, the barrier layer, the second n.sup.- channel region, the n.sup.+ drain regions, the insulating film, and the metal electrodes are successively deposited on the n.sup.+ crystal substrate in a growing apparatus. The metal electrodes and the source electrode are formed by depositing a metal and a low-resistance semiconductor selectively or both in one location within the growing apparatus.

摘要翻译： 半导体器件在各个n +漏极区域上具有n +源极区，第一n沟道区，势垒层，第二n沟道区，一对n +漏极区，绝缘膜和一对金属电极 ，全部依次设置在n +晶体基板的上表面上。 漏极区域和金属电极共同提供存储电容。 源电极设置在n +晶体基板的下表面上。 通过穿过阻挡层可以高速写入和读取位信息。 根据制造上述半导体器件的方法，依次沉积n +源极区，第一n-沟道区，势垒层，第二n-沟道区，n +漏极区，绝缘膜和金属电极 在生长装置中的n +晶体衬底上。 金属电极和源电极通过在生长装置内的一个位置中选择性地或两者沉积金属和低电阻半导体而形成。

公开(公告)号：US5475242A

公开(公告)日：1995-12-12

申请号：US425250

申请日：1995-04-17

申请人： Jun-ichi Nishizawa ,  Nobuo Takeda ,  Toshiyuki Kishine

发明人： Jun-ichi Nishizawa ,  Nobuo Takeda ,  Toshiyuki Kishine

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/33

CPC分类号： H01L27/092

摘要： A notched insulation gate static induction transistor integrated circuit ording to the present invention comprises an enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to prevent current from flowing in a standby mode, and a depletion enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to cause current to slightly flow in the standby mode. The enhancement mode CMOS logic circuit and the depletion enhancement mode CMOS logic circuit are formed on a major surface of a substrate, and the depletion enhancement mode CMOS logic circuit is used in a circuit in which an average power consumption in a switching operation is higher than that in the standby mode.

摘要翻译： 根据本发明的缺口绝缘栅静电感应晶体管集成电路包括增强模式CMOS逻辑电路，其包括其中确定阈值电压以防止电流在待机模式下流动的缺口绝缘栅静电感应晶体管，以及耗尽增强 模式CMOS逻辑电路，其包括在待机模式下确定阈值电压以使电流稍微流动的缺口绝缘栅静电感应晶体管。 增强模式CMOS逻辑电路和耗尽增强模式CMOS逻辑电路形成在衬底的主表面上，并且耗尽增强模式CMOS逻辑电路用于其中开关操作中的平均功耗高于 在待机模式下。

公开(公告)号：US5254207A

公开(公告)日：1993-10-19

申请号：US983331

申请日：1992-11-30

申请人： Jun-ichi Nishizawa ,  Toru Kurabayashi

发明人： Jun-ichi Nishizawa ,  Toru Kurabayashi

IPC分类号： C30B25/02 ,  C30B23/02 ,  C30B25/10 ,  C30B25/12 ,  C30B25/16 ,  H01L21/205

CPC分类号： C30B25/105 ,  C30B23/002 ,  C30B23/02 ,  C30B29/42

摘要： Material and impurity gases are introduced into a crystal growth chamber to grow a crystal film on a GaAs substrate. A light beam emitted from a variable-wavelength light source is applied to the crystal film being grown on the substrate while varying the wavelength of the light beam. The dependency, on the wavelength of the light beam, of the intensity of light reflected by the crystal film is measured, and an optimum wavelength is selected for measurement depending on the type of molecules adsorbed while the crystal film is being grown. Light is then applied at the optimum wavelength to the crystal film being grown, and a time-dependent change in the intensity of light reflected by the crystal film is measured. The rate at which the material gases are introduced into the crystal growth chamber is adjusted to control the growth rate of the crystal film, the composition ratio of a mixed crystal thereof, and the density of the impurity therein.

公开(公告)号：US5027180A

公开(公告)日：1991-06-25

申请号：US423661

申请日：1989-10-18

申请人： Jun-ichi Nishizawa ,  Hisao Kondoh

发明人： Jun-ichi Nishizawa ,  Hisao Kondoh

IPC分类号： H01L29/74 ,  H01L29/10 ,  H01L29/739

CPC分类号： H01L29/1066 ,  H01L29/7392

摘要： A double gate static induction thyristor comprises a semiconductor substrate, a first gate region formed at a first principal surface of the substrate, and a first semiconductor region of a first conduction type formed on the same first principal surface. A second gate region is formed at a second principal surface of the substrate, and a second semiconductor region of a second conduction type is formed on the same second principal surface. Gate electrodes are formed on the first and second gate regions, and main electrodes are formed on the first and second semiconductor regions, so that portions of the semiconductor regions surrounded by the gate regions form a current path between the main electrodes. Further, impurity is deeply diffused in portions of the first and second gate regions formed with the gate electrodes.

摘要翻译： 双栅极静电感应晶闸管包括半导体衬底，形成在衬底的第一主表面处的第一栅极区域和形成在相同的第一主表面上的第一导电类型的第一半导体区域。 第二栅极区域形成在基板的第二主表面处，并且第二导电类型的第二半导体区域形成在相同的第二主表面上。 栅电极形成在第一和第二栅极区上，并且主电极形成在第一和第二半导体区上，使得被栅极区包围的半导体区域的部分在主电极之间形成电流路径。 此外，在形成有栅电极的第一和第二栅极区域的部分中，杂质被深度扩散。

公开(公告)号：US5019876A

公开(公告)日：1991-05-28

申请号：US332441

申请日：1989-04-04

申请人： Jun-ichi Nishizawa

发明人： Jun-ichi Nishizawa

IPC分类号： H01L27/146 ,  H01L31/112

CPC分类号： H01L31/1126 ,  H01L27/14679

摘要： A high sensitivity semiconductor photo-electric converter is provided by electrically isolating the gate region of a static induction transistor which exhibits non-saturating current versus voltage characteristic. Optically ionized minority carriers are stored in the gate region to control the potential thereof. A semiconductor gate region provided with a insulated gate is very effective to enhance the dynamic range of the converter. Non-saturating characteristic enables enlargement of the output current simply by increasing the drain voltage. A high-speed and high sensitivity image pick-up device can be materialized by integrating a multiplicity of the static induction type photo-electric converter elements. A switching transistor may be merged in the gate region of each photo-electric converter element to enhance the operation speed of the image pick-up device.

摘要翻译： 通过电绝缘静电感应晶体管的栅极区域提供高灵敏度半导体光电转换器，其表现出非饱和电流对电压特性。 将光电离的少数载流子存储在栅极区域中以控制其电位。 设置有绝缘栅极的半导体栅极区域非常有效地增强了转换器的动态范围。 非饱和特性可以简单地通过增加漏极电压来扩大输出电流。 可以通过集成多个静电感应型光电转换器元件来实现高速和高灵敏度的图像拾取装置。 开关晶体管可以合并在每个光电转换器元件的栅极区域中，以增强图像拾取装置的操作速度。

公开(公告)号：US4935798A

公开(公告)日：1990-06-19

申请号：US47292

申请日：1987-05-08

申请人： Jun-ichi Nishizawa ,  Tadahiro Ohmi

发明人： Jun-ichi Nishizawa ,  Tadahiro Ohmi

IPC分类号： H01L29/80 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739 ,  H01L29/74

CPC分类号： H01L29/7392 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/1066 ,  H01L29/42312 ,  H01L29/7391

摘要： In a static induction type thyristor comprising a low impurity concentration channel region having opposed first and second major surfaces, a first main electrode region having one conductivity type and a second main electrode region having another conductivity type opposite to the one conductivity type and provided on the first and second major surfaces, respectively, and a gate region provided in the vicinity of the first main electrode region, there intervenes, between the channel region and the second main electrode region, a thin layer region having the same conductivity type as that of first main electrode region. The provision of this thin layer reegion contributes to allowing a markedly low impurity concentration as well as a decreased thickness of the channel region for a given maximum forward blocking voltage, making it feasible to obtain a high maximum forward blocking voltage and a high switching speed.

公开(公告)号：US4917757A

公开(公告)日：1990-04-17

申请号：US153567

申请日：1988-02-03

申请人： Jun-ichi Nishizawa

发明人： Jun-ichi Nishizawa

IPC分类号： C30B9/06 ,  C30B11/00 ,  C30B19/04 ,  C30B29/48 ,  H01L21/06

CPC分类号： C30B11/00 ,  C30B19/04 ,  C30B29/48 ,  Y10S438/925 ,  Y10S438/971

摘要： In a method of performing a solution growth of a ZnSe crystal using Se as a solvent and relying on the temperature difference technique, the growth is performed under the conditions that the vapor pressure of Zn which is lower than the vapor pressure of Se is applied, under controlled manner, to the solvent during the growth process, in which the value of the Zn vapor pressure is held constant at 7.2 atm. .+-.30%, whereby a ZnSe crystal having a good crystal perfection is obtained.

摘要翻译： 在使用Se作为溶剂并依靠温差技术进行ZnSe晶体的溶液生长的方法中，在施加低于Se的蒸气压的Zn的蒸气压的条件下进行生长， 在控制方式下，在生长过程中，Zn蒸汽压的值保持恒定在7.2atm的溶剂。 +/- 30％，由此获得具有良好晶体完整性的ZnSe晶体。