Input return path based on VDDQ/VSSQ
    61.
    发明申请
    Input return path based on VDDQ/VSSQ 有权
    基于VDDQ / VSSQ的输入返回路径

    公开(公告)号:US20050281074A1

    公开(公告)日:2005-12-22

    申请号:US10870100

    申请日:2004-06-17

    申请人: Jonghee Han

    发明人: Jonghee Han

    IPC分类号: G11C5/14 G11C11/24

    CPC分类号: G11C5/14

    摘要: Input circuit configurations that reduce the amount of input signal jitter caused by a common input signal return path, methods and circuits utilizing the same are provided. Input signal return path noise may be decoupled from the power for receiver circuits, for example, by utilizing separate power supply lines, such as VDDQ and VSSQ, as input signal return path.

    摘要翻译: 提供了减少由公共输入信号返回路径引起的输入信号抖动量的输入电路配置,使用其的方法和电路。 输入信号返回路径噪声可以与接收机电路的功率分离,例如通过使用诸如V DDQ和V SSQ之类的单独电源线作为输入信号 返回路径。

    Separator for fuel cell using a metal plate coated with titanium nitride, method for manufacturing the same, and polymer electrolyte membrane fuel cell comprising the separator
    62.
    发明申请
    Separator for fuel cell using a metal plate coated with titanium nitride, method for manufacturing the same, and polymer electrolyte membrane fuel cell comprising the separator 有权
    使用涂有氮化钛的金属板的燃料电池分离器,其制造方法以及包含该隔板的高分子电解质膜燃料电池

    公开(公告)号:US20050214618A1

    公开(公告)日:2005-09-29

    申请号:US11011589

    申请日:2004-12-13

    摘要: Disclosed is a separator for a fuel cell made of a metal plate coated with TiN, a polymer electrolyte membrane fuel cell comprising the separator and a method for manufacturing the separator. According to the invention, the separator can be made to be thin and it is possible to increase the power density, compared to the prior separator made of graphite. At the same time, a proper level of physical strength can be maintained, so that there is no problem of a breakdown by an external shock. In addition, the flow field can be easily formed and the cost is low. Additionally, the polymer electrolyte membrane fuel cell comprising the separator using a metal plate coated with TiN according to the invention has no problem of corrosion of metal separator due to the electrolyte, compared to the prior metal separator, so that the durability is excellent and the lifetime is long. In addition, when a mass-production system is established, the flow fields are provided by stamping a thin metal plate instead of forming the flow fields on the stainless steel plate, and then the two plates are brazed and coated with TiN, so that the weight of the stack is decreased.

    摘要翻译: 公开了一种由涂覆有TiN的金属板制成的燃料电池用隔膜,包含隔膜的高分子电解质膜燃料电池及其制造方法。 根据本发明,与现有的由石墨制成的隔板相比,可以使隔板变薄,并且可以提高功率密度。 同时,可以保持适当的体力水平,以免外部冲击而发生故障。 此外,流场可以容易地形成并且成本低。 此外,与现有的金属隔板相比,包含使用根据本发明的涂覆有TiN的金属板的隔板的聚合物电解质膜燃料电池没有由于电解质而导致的金属隔板的腐蚀的问题,从而耐久性优异, 一生多久 此外,当建立批量生产系统时,通过冲压薄金属板来提供流场,而不是在不锈钢板上形成流场,然后将两个板钎焊并涂覆TiN,使得 堆的重量减少。

    Method and circuit configuration for digitizing a signal in an input buffer of a DRAM device
    63.
    发明授权
    Method and circuit configuration for digitizing a signal in an input buffer of a DRAM device 失效
    用于数字化DRAM设备的输入缓冲器中的信号的方法和电路配置

    公开(公告)号:US06934197B2

    公开(公告)日:2005-08-23

    申请号:US10683768

    申请日:2003-10-10

    申请人: Jonghee Han

    发明人: Jonghee Han

    IPC分类号: G11C5/00 G11C7/10 G11C16/04

    CPC分类号: G11C7/1084 G11C7/1078

    摘要: A method and circuit configuration for digitizing data and control signals using an input buffer in a dynamic random access memory (DRAM) device. In one embodiment, the input buffer includes buffer modules having a differential amplifier with a first input responsive to an input signal and a second input responsive to a reference voltage, a common source stage, and an output stage and a source of a bias voltage controlling impedance of the common source stage, wherein the reference voltage defines the amplitude of the bias voltage.

    摘要翻译: 一种用于使用动态随机存取存储器(DRAM)装置中的输入缓冲器数字化数据和控制信号的方法和电路配置。 在一个实施例中,输入缓冲器包括缓冲器模块,其具有响应于输入信号的具有第一输入的差分放大器和响应于参考电压的第二输入,公共源级和输出级以及偏置电压控制源 公共源级的阻抗,其中参考电压限定偏置电压的幅度。

    Multiple data rate bus using return clock
    64.
    发明申请
    Multiple data rate bus using return clock 审中-公开
    多数据速率总线使用返回时钟

    公开(公告)号:US20050097291A1

    公开(公告)日:2005-05-05

    申请号:US10699473

    申请日:2003-10-31

    申请人: Jonghee Han

    发明人: Jonghee Han

    IPC分类号: G11C7/10 G06F12/00

    摘要: A method and apparatus for ensuring safe transmission of data on a bus line. In one embodiment, within a given clock period, first data is driven on a data bus and a strobe signal is transmitted, via a first signal path, to a receiving circuit indicating the validity of the first data on the data bus. A return signal received within the given clock period indicates an assumed arrival of the strobe signal at the receiving circuit. In response to receiving the return signal, second data is driven onto the data bus.

    摘要翻译: 一种用于确保总线上数据安全传输的方法和装置。 在一个实施例中,在给定的时钟周期内,第一数据在数据总线上被驱动,并且选通信号经由第一信号路径被发送到指示数据总线上的第一数据的有效性的接收电路。 在给定时钟周期内接收到的返回信号表示选通信号在接收电路处的假定到达。 响应于接收到返回信号,第二数据被驱动到数据总线上。

    Dual power sensing scheme for a memory device
    65.
    发明授权
    Dual power sensing scheme for a memory device 失效
    用于存储器件的双功率感测方案

    公开(公告)号:US06888767B1

    公开(公告)日:2005-05-03

    申请号:US10723211

    申请日:2003-11-26

    申请人: Jonghee Han

    发明人: Jonghee Han

    摘要: Sensing operations involving a first array of bit line sense amplifiers (BLSAs) may be powered by an upper reference voltage and a first intermediate voltage and the first array may be precharged to a voltage level therebetween. Sensing operations involving a second array of BLSAs may be powered by a second intermediate voltage (greater than the first intermediate voltage) and a lower reference voltage and the second array may be precharged to a voltage level therebetween. After precharge, charge may be transferred from a second power line of the first array to a first power line of the second array. Subsequently, the second power line of the first array may be coupled to a power supply node at the first intermediate voltage level and the first power line of the second array may be coupled to a power supply node at the second intermediate voltage level.

    摘要翻译: 涉及第一阵列位线读出放大器(BLSA)的感测操作可以由上参考电压和第一中间电压供电,并且第一阵列可以被预充电到它们之间的电压电平。 涉及第二阵列BLSA的感测操作可以由第二中间电压(大于第一中间电压)供电,并且较低的参考电压和第二阵列可以被预充电到它们之间的电压电平。 在预充电之后,电荷可以从第一阵列的第二电力线转移到第二阵列的第一电力线。 随后,第一阵列的第二电源线可以耦合到处于第一中间电压电平的电源节点,并且第二阵列的第一电源线可以耦合到处于第二中间电压电平的电源节点。

    Method and circuit configuration for digitizing a signal in an input buffer of a DRAM device

    公开(公告)号:US20050078530A1

    公开(公告)日:2005-04-14

    申请号:US10683768

    申请日:2003-10-10

    申请人: Jonghee Han

    发明人: Jonghee Han

    IPC分类号: G11C5/00 G11C7/10 G11C16/04

    CPC分类号: G11C7/1084 G11C7/1078

    摘要: A method and circuit configuration for digitizing data and control signals using an input buffer in a dynamic random access memory (DRAM) device. In one embodiment, the input buffer includes buffer modules having a differential amplifier with a first input responsive to an input signal and a second input responsive to a reference voltage, a common source stage, and an output stage and a source of a bias voltage controlling impedance of the common source stage, wherein the reference voltage defines the amplitude of the bias voltage.

    Laundry treating apparatus
    67.
    发明授权
    Laundry treating apparatus 有权
    洗衣处理设备

    公开(公告)号:US09388523B2

    公开(公告)日:2016-07-12

    申请号:US13600973

    申请日:2012-08-31

    摘要: An apparatus includes a first device to perform a first laundry treating operation and a second device to perform a second laundry treating operation. The first device has a first space to receive laundry through a first opening and the second device has a second space to receive laundry through a second opening. A controller controls the first and second devices to perform the first and second laundry treating operations respectively. The first device is coupled over the first device, and the first and second laundry treating operations are both washing operations or the first and second laundry treating operations are both drying operations.

    摘要翻译: 一种装置包括执行第一衣物处理操作的第一装置和执行第二衣物处理操作的第二装置。 第一装置具有通过第一开口接收衣物的第一空间,并且第二装置具有通过第二开口接收衣物的第二空间。 控制器控制第一和第二装置分别执行第一和第二衣物处理操作。 第一装置连接在第一装置上,并且第一和第二衣物处理操作都是洗涤操作,或者第一和第二衣物处理操作都是干燥操作。

    System and method to synchronize signals in individual integrated circuit components
    70.
    发明授权
    System and method to synchronize signals in individual integrated circuit components 有权
    在单个集成电路组件中同步信号的系统和方法

    公开(公告)号:US07405996B2

    公开(公告)日:2008-07-29

    申请号:US11408647

    申请日:2006-04-21

    IPC分类号: G11C8/00

    摘要: A synchronous output signal generated by an integrated circuit (IC) component is synchronized to an applied clock signal for each individual IC component. A variable feedback delay in the IC component is incrementally altered to alter the phase skew between the clock signal and the output signal. The relative phase order of the clock and output signals is monitored in the IC component. In response to detecting a swap in the relative phase order of the clock and output signals, the variable feedback delay ceases to be altered. In some embodiments, the IC component may be a SDRAM component.

    摘要翻译: 由集成电路(IC)组件产生的同步输出信号与用于每​​个单独IC组件的所施加的时钟信号同步。 逐渐改变IC组件中的可变反馈延迟,以改变时钟信号和输出信号之间的相位偏移。 在IC组件中监视时钟和输出信号的相对相位顺序。 响应于检测到时钟和输出信号的相对相位顺序的交换,可变反馈延迟不再改变。 在一些实施例中,IC组件可以是SDRAM组件。