公开(公告)号：US20090052153A1

公开(公告)日：2009-02-26

申请号：US11844397

申请日：2007-08-24

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC: H05K9/00

CPC classification number: H05K9/0022

Abstract: An electromagnetic shielding structure that includes a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate. At least one feed through device is associated with the conductive structure and provides signals to the circuit or circuit device. The method includes forming a shielding structure so that the shielding structure at least one of is at least partially arranged within the substrate and surrounds the circuit or circuit device and associating at least one feed through device with the shielding structure.

Abstract translation: 一种电磁屏蔽结构，其包括围绕并容纳布置在基板上的电路或电路装置的导电结构。 至少一个馈送装置与导电结构相关联，并向电路或电路装置提供信号。 所述方法包括形成屏蔽结构，使得所述屏蔽结构至少部分地至少部分地布置在所述基板内并且围绕所述电路或电路装置并且将至少一个馈送装置与所述屏蔽结构相关联。

公开(公告)号：US20080018411A1

公开(公告)日：2008-01-24

申请号：US11458215

申请日：2006-07-18

Applicant: Kai D. Feng ,  Anjali R. Malladi

Inventor： Kai D. Feng ,  Anjali R. Malladi

IPC: H03B5/12

CPC classification number: H03L7/087 ,  H03L7/10 ,  H03L2207/06

Abstract: The invention comprises a phase locked loop that has an input adapted to receive a reference frequency. A phase detector is connected directly to the input, a charge pump is connected directly to the phase detector, and a loop filter is connected directly to the charge pump. Also, a voltage controlled oscillator is connected directly to the loop filter, and is adapted to perform frequency band selection. A band selection circuit is connected to the voltage controlled oscillator.

Abstract translation: 本发明包括具有适于接收参考频率的输入的锁相环。 相位检测器直接连接到输入端，电荷泵直接连接到相位检测器，环路滤波器直接连接到电荷泵。 此外，压控振荡器直接连接到环路滤波器，并且适于执行频带选择。 带选择电路连接到压控振荡器。

公开(公告)号：US07288417B2

公开(公告)日：2007-10-30

申请号：US10905480

申请日：2005-01-06

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC: H01L21/00

CPC classification number: H01L23/5227 ,  H01F17/0006 ,  H01F41/046 ,  H01F2019/085 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A mixed-signal chip having a signal transformer located between analog circuitry and digital circuitry. The signal transformer includes a primary winding electrically coupled to the analog circuitry and a secondary winding electrically coupled to the digital circuitry. The primary and secondary windings are magnetically coupled with one another via a magnetic core. The magnetic coupling between the primary and secondary windings inhibits the coupling of electrical noise between the analog and digital circuitries.

Abstract translation: 混合信号芯片，具有位于模拟电路和数字电路之间的信号变压器。 信号变压器包括电耦合到模拟电路的初级绕组和电耦合到数字电路的次级绕组。 初级和次级绕组通过磁芯彼此磁耦合。 初级和次级绕组之间的磁耦合阻碍了模拟和数字电路之间的电气噪声耦合。

公开(公告)号：US07071530B1

公开(公告)日：2006-07-04

申请号：US10905934

申请日：2005-01-27

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC: H01L21/762

CPC classification number: H01L21/76264 ,  H01L23/552 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure, comprising: providing a substrate having a buried insulative layer and a heavily doped layer; forming a first trench within the substrate around a protected area; filling the first trench with an insulative material, wherein the first trench filled with the insulative material and the buried insulative layer combine to form a high impedance noise isolation that surrounds the protected area on all sides except one side of the protected area to isolate noise from the protected area; forming a second trench within the substrate around the first trench; and filling the second trench with a conductive material, wherein the second trench filled with the conductive material and the heavily doped layer combine to form a low impedance ground path that surrounds the high impedance noise isolation on all sides except one side of the high impedance noise isolation to isolate noise from the protected area.

Abstract translation: 一种形成半导体结构的方法，包括：提供具有掩埋绝缘层和重掺杂层的衬底; 在保护区域周围形成衬底内的第一沟槽; 用绝缘材料填充第一沟槽，其中填充有绝缘材料的第一沟槽和埋入绝缘层组合形成高阻抗噪声隔离，围绕保护区域的保护区域，除了保护区域的一侧以隔离噪声 保护区; 在所述衬底内围绕所述第一沟槽形成第二沟槽; 以及用导电材料填充所述第二沟槽，其中填充有所述导电材料和所述重掺杂层的所述第二沟槽组合以形成低阻抗接地路径，所述低阻抗接地路径围绕除所述高阻抗噪声的一侧之外的所有侧面上的高阻抗噪声隔离 隔离隔离来自保护区的噪音。

公开(公告)号：US06914467B2

公开(公告)日：2005-07-05

申请号：US10729779

申请日：2003-12-04

Applicant: Kai D. Feng ,  Hongfei Wu

Inventor： Kai D. Feng ,  Hongfei Wu

IPC: H03K5/14 ,  G01R1/00 ,  H03H11/26 ,  H03K5/00 ,  H03K5/06 ,  H03K5/13 ,  H03K5/1532 ,  H03K17/693 ,  H03K19/0948 ,  H03K19/173

CPC classification number: H03K5/06 ,  H03K5/13 ,  H03K2005/00058 ,  H03K2005/00293

Abstract: A method and device program a dual edge programmable delay unit, that responds to an input signal with a rise time and a fall time, includes a buffer which receives the input signal and provides an output signal with programmed variable delays between the rise and fall times of the output signal. Programmable control sources (PCS) provide separate control inputs to a buffer. The FTPCS charges a capacitor in the buffer when the input signal changes from high to low to adjust time delay before the fall of the buffer output signal. The RTPCS discharges the capacitor in the buffer when the input signal changes from low to high to adjust time delay before the rise of the buffer output signal.

Abstract translation: 一种双边缘可编程延迟单元的方法和装置程序，其响应于上升时间和下降时间的输入信号，包括缓冲器，其接收输入信号并在上升和下降时间之间提供编程的可变延迟的输出信号 的输出信号。 可编程控制源（PCS）为缓冲区提供单独的控制输入。 当输入信号从高电平变为低电平时，FTPCS在缓冲器中为电容器充电，以在缓冲器输出信号下降之前调整时间延迟。 当输入信号从低电平变为高电平时，RTPCS会在缓冲器中放电电容，以调整缓冲器输出信号上升之前的时间延迟。

公开(公告)号：US06842044B1

公开(公告)日：2005-01-11

申请号：US10692192

申请日：2003-10-23

Applicant: Kai D. Feng ,  Hongfei Wu

Inventor： Kai D. Feng ,  Hongfei Wu

IPC: H03K5/00 ,  H03K5/1252 ,  H03K5/13 ,  H03K17/16 ,  H04L5/14 ,  H04L25/06 ,  H03K19/0175

CPC classification number: H04L25/068 ,  H03K5/1252 ,  H03K5/133 ,  H03K17/164 ,  H03K2005/00065 ,  H03K2005/00195 ,  H04L5/1423

Abstract: A structure and method for eliminating glitches at the output of a receiver receiving signals sent to one end of a bi-directional, simultaneous transmission line. The receiver comprises two comparators, a logic circuit, a glitch detector, and a programmable delay unit. The two comparators convert a three-state digital signal on the transmission line into two two-state digital signals so that the logic circuit can understand. When a glitch occurs at the output of the logic circuit, also the output of the receiver, caused by the transitions on the output of one of the comparators and a first signal being sent to the other end of the transmission line reaching the logic circuit not at the same time, the glitch detector causes the programmable delay unit to adjust delay to the propagation path of the first signal to the logic circuit so as to eliminate the cause of the glitch.

Abstract translation: 一种用于消除在接收发送到双向同时传输线路的一端的信号的接收机的输出处的毛刺的结构和方法。 接收机包括两个比较器，逻辑电路，毛刺检测器和可编程延迟单元。 两个比较器将传输线上的三态数字信号转换为两个双状态数字信号，使得逻辑电路可以理解。 当在逻辑电路的输出端发生毛刺时，由比较器之一的输出上的转换引起的接收器的输出以及发送到传输线的另一端的第一信号到达逻辑电路 同时，毛刺检测器使可编程延迟单元调整到第一信号到逻辑电路的传播路径的延迟，以消除毛刺的原因。

公开(公告)号：US08618839B2

公开(公告)日：2013-12-31

申请号：US13418961

申请日：2012-03-13

Applicant: Howard H. Chi ,  Haitao O. Dai ,  Kai D. Feng ,  Donald J. Papae

Inventor： Howard H. Chi ,  Haitao O. Dai ,  Kai D. Feng ,  Donald J. Papae

IPC: G01R19/00

CPC classification number: H03F3/45183 ,  H03F3/45609 ,  H03F3/68 ,  H03F2200/408 ,  H03F2200/78

Abstract: Embodiments of the present invention provide an approach for utilizing a sense amplifier to select a suitable circuit, wherein a suitable circuit generates a voltage that is greater than or equal to a configurable reference voltage. An amplifier gain selector selects a voltage gain of a sense amplifier having input terminals, auxiliary inputs, an output, an array of resistive loads, and the amplifier gain selector. Auxiliary inputs are utilized to nullify direct current (DC) offset voltage of the sense amplifier. Combinatorial logic circuitry connects the input terminals of the sense amplifier to output terminals of a circuit that is within a group of circuits. A comparator circuit determines if the circuit generates a voltage greater than or equal to a configurable reference voltage, based on the output of the sense amplifier.

Abstract translation: 本发明的实施例提供了一种利用读出放大器来选择合适电路的方法，其中合适的电路产生大于或等于可配置参考电压的电压。 放大器增益选择器选择具有输入端，辅助输入，输出，电阻性负载阵列和放大器增益选择器的读出放大器的电压增益。 辅助输入用于消除读出放大器的直流（DC）偏移电压。 组合逻辑电路将读出放大器的输入端连接到一组电路内的电路的输出端。 比较器电路基于读出放大器的输出来确定电路是否产生大于或等于可配置参考电压的电压。

公开(公告)号：US08493075B2

公开(公告)日：2013-07-23

申请号：US12877159

申请日：2010-09-08

Applicant: Kai D. Feng ,  Jong-Ru Guo ,  Ping-Chuan Wang ,  Zhijian Yang

Inventor： Kai D. Feng ,  Jong-Ru Guo ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: G01R31/00

CPC classification number: H03K19/00369

Abstract: An embedded decoupling capacitor wearout monitor for power transmission line, which can be integrated and fabricated in any standard CMOS or BiCMOS circuits. The embedded noise monitor is employed to detect the degraded capacitor and disable it from further operation, which will extend the operation lifetime of the circuit system and prevent subsequent catastrophic failure as a result of hard-breakdown (or capacitor short). In one aspect, the monitor circuit and method detects early degradation signal before catastrophic decoupling capacitor failure and, further can pin-point a degraded decoupling capacitor and disable it, avoiding impact from decoupling capacitor breakdown failure. The monitor circuit and method provides for decoupling capacitor redundancy and includes an embedded and self-diagnostic circuit for functionality and reliability.

Abstract translation: 用于输电线路的嵌入式去耦电容器损耗监测器，可以在任何标准CMOS或BiCMOS电路中集成和制造。 嵌入式噪声监测器用于检测劣化的电容器，并禁止其进一步操作，这将延长电路系统的工作寿命，并防止由于硬击穿（或电容器短路）引起的灾难性故障。 在一个方面，监测电路和方法在灾难性去耦电容器故障之前检测早期劣化信号，并且还可以对劣化的去耦电容进行引脚定位并使其失效，避免去耦电容器击穿故障的影响。 监控电路和方法提供了去耦电容冗余，并且包括用于功能和可靠性的嵌入式和自诊断电路。

公开(公告)号：US08471595B1

公开(公告)日：2013-06-25

申请号：US13353383

申请日：2012-01-19

Applicant: John S. Austin ,  Kai D. Feng ,  Shiu Chung Ho ,  Zhenrong Jin ,  Michael R. Ouellette

Inventor： John S. Austin ,  Kai D. Feng ,  Shiu Chung Ho ,  Zhenrong Jin ,  Michael R. Ouellette

IPC: G06F7/38 ,  H03K19/173

CPC classification number: H03K3/35606 ,  G06F7/68 ,  H03K19/1737

Abstract: A selectable latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. The output of the parallel pass gates and the additional pass gate is connected to a feedback loop. The feedback loop operates as a dynamic latch for high frequency applications or as a static latch for low frequency applications. Thus, the selectable latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal.

Abstract translation: 可选择的锁存器具有一对并行通过门（接收种子信号的第一并行通道门和接收数据信号的第二并行通道门）。 第一锁存逻辑电路使用由并行通道门输出的信号来执行逻辑运算以产生更新的数据信号。 附加的通过门可操作地连接到第一锁存逻辑电路。 一个附加的传递门控制更新的数据信号的通过。 并联栅极和附加栅极的输出端连接到反馈回路。 反馈回路作为高频应用的动态锁存器或作为低频应用的静态锁存器。 因此，可选择的锁存器包括两个输入到该对并行通道门中，并且仅对接收的数据信号执行四个逻辑运算中的一个。

公开(公告)号：US20130106452A1

公开(公告)日：2013-05-02

申请号：US13282090

申请日：2011-10-26

Applicant: Fen Chen ,  Roger A. Dufresne ,  Kai D. Feng ,  Richard J. St-Pierre

Inventor： Fen Chen ,  Roger A. Dufresne ,  Kai D. Feng ,  Richard J. St-Pierre

IPC: G01R31/3187

CPC classification number: G01R31/3004

Abstract: An integrated circuit, testing structure, and method for monitoring electro-migration (EM) performance. A method is described that includes method for measuring on-chip electro-migration (EM) performance, including: providing a first on-chip sensor continuously powered with a stress current; providing a second on-chip sensor that is powered only during measurement cycles with a nominal current; obtaining a first resistance measurement from the first on-chip sensor and a second resistance measurement from the second on-chip sensor during each of a series of measurement cycles; and processing the first and second resistance measurements.

Abstract translation: 用于监测电迁移（EM）性能的集成电路，测试结构和方法。 描述了一种包括用于测量片上电迁移（EM）性能的方法的方法，包括：提供用应力电流连续供电的第一片上传感器; 提供仅在具有额定电流的测量周期期间供电的第二片上传感器; 在一系列测量周期中的每一个期间，从第一片上传感器获得第一电阻测量值和来自第二片上传感器的第二电阻测量值; 并处理第一和第二电阻测量。