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61.发明授权公开(公告)号：US07925825B2
公开(公告)日：2011-04-12
申请号：US12019071
申请日：2008-01-24
IPC分类号： G06F12/00
CPC分类号： G06F13/4243
摘要： A memory system is provided that implements an asynchronous boundary in a memory module. The memory system comprises a memory hub device integrated in a memory module. The memory system also comprises a set of memory devices coupled to the memory hub device. The memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency. The memory system further comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented within the memory hub device of the memory module.
摘要翻译： 提供了一种在存储器模块中实现异步边界的存储器系统。 存储器系统包括集成在存储器模块中的存储器集线器设备。 存储器系统还包括耦合到存储器集线器设备的一组存储器件。 存储器集线器设备包括命令队列，其经由存储器通道以第一工作频率从外部存储器控制器接收存储器访问命令。 存储器系统还包括集成在存储器集线器设备中的存储器集线器控制器。 存储器集线器控制器以第二工作频率从命令队列读取存储器访问命令。 通过以第一工作频率接收存储器访问命令并且以第二工作频率读取存储器访问命令，在存储器模块的存储器集线器设备内实现异步边界。
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公开(公告)号：US20110075740A1
公开(公告)日：2011-03-31
申请号：US12568765
申请日：2009-09-29
IPC分类号： H04B3/00
CPC分类号： H04L25/0272 , Y02D30/30
摘要： An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.
摘要翻译： 一种在第一和第二电子单元之间具有功率有效的差分信号的电子系统。 控制器使用诸如符合数据传输速率要求和误码率（BER）与BER阈值的信息来控制功率模式，使得需要最小量的功率。 传输幅度和数据的单端或差分传输是功率模式的例子。 控制器还在选择满足BER阈值的传输速率要求的最小功率模式时，在差分信号中导致故障相位。
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63.发明申请ADVANCED MEMORY DEVICE HAVING IMPROVED PERFORMANCE, REDUCED POWER AND INCREASED RELIABILITY 有权具有改进性能，降低功耗和提高可靠性的高级存储设备公开(公告)号：US20110055671A1
公开(公告)日：2011-03-03
申请号：US12553400
申请日：2009-09-03
申请人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
发明人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
CPC分类号： G11C7/1078 , G06F11/1028 , G11C7/04 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C11/4076 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
摘要翻译： 具有改进性能，降低功耗和增加可靠性的高级内存。 存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路 对错误控制编码电路检测接收到的命令中的错误。 另一个存储器件包括可编程序序。 另一存储器件包括快速退出自刷新模式。 另一种存储装置包括由特征装置控制的自动刷新功能。 另一存储器件包括由存储器件的特性控制的自动刷新功能。
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64.发明授权System, method and storage medium for a memory subsystem command interface 失效用于内存子系统命令界面的系统，方法和存储介质公开(公告)号：US07844771B2
公开(公告)日：2010-11-30
申请号：US12059164
申请日：2008-03-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
CPC分类号： G06F13/1684
摘要： A system for implementing a memory subsystem command interface, the system including a cascaded interconnect system including one or more memory modules, a memory controller and a memory bus. The memory controller generates a data frame that includes a plurality of commands. The memory controller and the memory module are interconnected by a packetized multi-transfer interface via the memory bus and the frame is transmitted to the memory modules via the memory bus.
摘要翻译： 一种用于实现存储器子系统命令接口的系统，该系统包括包括一个或多个存储器模块，存储器控制器和存储器总线的级联互连系统。 存储器控制器生成包括多个命令的数据帧。 存储器控制器和存储器模块通过存储器总线通过分组化的多传输接口互连，并且帧经由存储器总线传送到存储器模块。
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65.发明申请Memory System having Spare Memory Devices Attached to a Local Interface Bus 审中-公开具有连接到本地接口总线的备用内存设备的内存系统公开(公告)号：US20100162037A1
公开(公告)日：2010-06-24
申请号：US12341472
申请日：2008-12-22
CPC分类号： G06F13/1684 , G06F11/106 , G11C5/04 , G11C29/83 , Y02D10/14
摘要： A memory system includes a memory controller, one or more memory channel(s), and a memory subsystem having a memory interface device (e.g. a hub or buffer device) located on a memory subsystem (e.g. a DIMM) coupled to the memory channel to communicate with the memory device(s) array. This buffered DIMM is provided with one or more spare chips on the DIMM, wherein the data bits sourced from the spare chips are connected to the memory hub device and the bus to the DIMM includes only those data bits used for normal operation. The buffered DIMM with one or more spare chips on the DIMM has the spare memory shared among all the ranks, and the memory hub device includes separate control bus(es) for the spare memory device to allow the spare memory device(s) to be utilized to replace one or more failing bits and/or devices within any rank of memory in the memory subsystem.
摘要翻译： 存储器系统包括存储器控制器，一个或多个存储器通道和存储器子系统，该存储器子系统具有位于耦合到存储器通道的存储器子系统（例如，DIMM）上的存储器接口设备（例如，集线器或缓冲设备） 与存储器件阵列通信。 该缓冲DIMM在DIMM上提供一个或多个备用芯片，其中从备用芯片获取的数据位连接到存储器集线器设备，并且到DIMM的总线仅包括用于正常操作的那些数据位。 在DIMM上具有一个或多个备用芯片的缓冲DIMM具有在所有等级中共享的备用存储器，并且存储器集线器设备包括用于备用存储器设备的单独的控制总线，以允许备用存储器设备 用于替换存储器子系统中的任何等级的存储器内的一个或多个故障位和/或设备。
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66.发明申请Power Management of a Spare DRAM on a Buffered DIMM by Issuing a Power On/Off Command to the DRAM Device 失效通过向DRAM器件发出电源开/关命令，对缓冲DIMM上的备用DRAM进行电源管理公开(公告)号：US20100162020A1
公开(公告)日：2010-06-24
申请号：US12341515
申请日：2008-12-22
CPC分类号： G11C5/06 , G11C5/04 , G11C5/14 , G11C11/4074
摘要： A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.
摘要翻译： 一种具有一个或多个具有内部存储器阵列的半导体存储器件的计算机存储器，所述内部存储器阵列包括排列成行和列的矩阵的多个半导体动态随机存取存储器（DRAM）单元，并被提供为这种存储器的存储器模块等级 在基板上的一个或多个所述半导体存储器件的DIMM上布置的阵列中的器件，其可以经由存储器件数据接口耦合到作为存储器子系统的存储器系统，每个所述存储器件具有低功率闭合 - 可以使用公共存储器数据接口激活。 通过数据接口对DRAM的功率的控制问题DRAM功率控制命令的两个命令解码，功率状态程序信号和功率状态复位信号作为功率状态控制命令来控制所述DRAM的功率状态， 并激活用于将存储器单元作为正常的有源或备用设备读/写。
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公开(公告)号：US20100005349A1
公开(公告)日：2010-01-07
申请号：US12165848
申请日：2008-07-01
IPC分类号： G06F11/00
CPC分类号： G06F11/2007 , G06F11/0724 , G06F11/076 , H04L1/20
摘要： A processing device, processing system, method, and design structure for an enhanced microprocessor interconnect with bit shadowing are provided. The processing device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The processing device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译： 提供了一种用于具有位阴影的增强型微处理器互连的处理装置，处理系统，方法和设计结构。 处理装置包括阴影选择逻辑以选择驱动器位位置作为阴影驱动器值，以及线驱动器，用于在总线的单独链路段上传送所选择的驱动器位位置和阴影驱动器值的数据。 处理装置还包括阴影比较逻辑，以将所选接收值与来自总线的阴影接收值进行比较，并根据比较不匹配识别错误比较，并且阴影计数器计数误差相对于总线误差的速率 率一段时间。 响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。
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公开(公告)号：US20100005218A1
公开(公告)日：2010-01-07
申请号：US12165816
申请日：2008-07-01
IPC分类号： G06F12/06
CPC分类号： G06F13/4234
摘要： A system, memory hub device, method and design structure for providing an enhanced cascade interconnected memory system are provided. The system includes a memory controller, a memory channel, a memory hub device coupled to the memory channel to communicate with the memory controller via one of a direct connection and a cascade interconnection through another memory hub device, and multiple memory devices in communication with the memory controller via one or more cascade interconnected memory hub devices. The memory channel includes unidirectional downstream link segments coupled to the memory controller and operable for transferring configurable data frames. The memory channel further includes unidirectional upstream link segments coupled to the memory controller and operable for transferring data frames.
摘要翻译： 提供了一种用于提供增强级联互连存储器系统的系统，存储器集线器设备，方法和设计结构。 该系统包括存储器控制器，存储器通道，耦合到存储器通道的存储器集线器设备，以经由另一个存储器集线器设备的直接连接和级联互连中的一个与存储器控制器进行通信，以及与存储控制器通信的多个存储器设备 存储器控制器经由一个或多个级联互连的存储器集线器设备。 存储器通道包括耦合到存储器控制器并且可操作用于传输可配置数据帧的单向下游链路段。 存储器通道还包括耦合到存储器控制器并且可操作用于传送数据帧的单向上游链路段。
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公开(公告)号：US20100005214A1
公开(公告)日：2010-01-07
申请号：US12165814
申请日：2008-07-01
CPC分类号： G06F13/405 , G06F13/4243 , G06F13/4256 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for enhancing bus efficiency and utilization in a memory system. The communication interface device includes a first bus interface to communicate on a high-speed bus, a second bus interface to communicate on a lower-speed bus, and clock ratio logic configurable to support multiple clock ratios between the high-speed bus and the lower-speed bus. The clock ratio logic reduces a high-speed clock frequency received at the first bus interface and outputs a reduced ratio of the high-speed clock frequency on the lower-speed bus via the second bus interface supporting variable frame sizes.
摘要翻译： 一种用于提高存储系统中总线效率和利用率的通信接口设备，系统，方法和设计结构。 通信接口设备包括用于在高速总线上通信的第一总线接口，用于在低速总线上进行通信的第二总线接口以及可配置为支持高速总线与低速总线之间的多个时钟比的时钟比率逻辑 高速公交车 时钟比率逻辑降低了在第一总线接口处接收的高速时钟频率，并且经由支持可变帧大小的第二总线接口输出低速总线上的高速时钟频率的减小的比率。
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70.发明申请276-PIN BUFFERED MEMORY MODULE WITH ENHANCED MEMORY SYSTEM INTERCONNECT AND FEATURES 有权具有增强的存储器系统的276引脚缓冲存储器模块互连和特性公开(公告)号：US20100003837A1
公开(公告)日：2010-01-07
申请号：US12166227
申请日：2008-07-01
IPC分类号： H01R12/00
CPC分类号： G11C5/04 , H01R12/721
摘要： A memory subsystem system including a rectangular printed circuit card having a first side and a second side, a length of between 149.5 and 153.5 millimeters, and first and second ends having a width smaller than the length. The memory system also includes a first plurality of pins on the first side extending along a first edge of the card that extends the length of the card, and a second plurality of pins on the second side extending on the first edge of the card. The memory system further includes a positioning key having it center positioned on the first edge of the card and located between 84.5 and 88.5 millimeters from the first end of the card and located between 62.5 and 66.5 millimeters from the second end of the card.
摘要翻译： 一种存储器子系统，包括具有第一侧和第二侧的矩形印刷电路卡，长度在149.5和153.5毫米之间，第一和第二端具有小于该长度的宽度。 存储器系统还包括在第一侧上沿着延长卡的长度的卡的第一边缘延伸的第一多个销，以及在卡的第一边缘上延伸的第二侧上的第二多个销。 存储系统还包括定位键，其中心位于卡的第一边缘上，并位于距离卡的第一端84.5至88.5毫米之间，并位于距卡的第二端62.5至66.5毫米之间。
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