公开(公告)号：US06389063B1

公开(公告)日：2002-05-14

申请号：US09182219

申请日：1998-10-30

申请人： Nobuyasu Kanekawa ,  Kazuo Kato ,  Yasuyuki Kojima ,  Seigoh Yukitake

发明人： Nobuyasu Kanekawa ,  Kazuo Kato ,  Yasuyuki Kojima ,  Seigoh Yukitake

IPC分类号： H04B138

CPC分类号： H04L1/0041 ,  H04L1/0045 ,  H04L25/0266

摘要： The signal x to be transmitted is converted to the redundant code f(x) by the redundancy coder 6 and transmitted via the isolating capacitor 2 of the isolator 50. When the signal f(x) redundancy-coded and transmitted is the coded word f(xi), the decoder 7 outputs xi which is inferred as an equivalent original signal and when an error occurs and the signal f(x) does not match the coded word f(xi), the decoder 7 corrects the error and outputs xi which is inferred as an original signal.

摘要翻译： 要发送的信号x被冗余编码器6转换成冗余码f（x），并通过隔离器50的隔离电容器2传输。当冗余编码和发送的信号f（x）是编码字f （xi）中，解码器7输出被推定为等效原始信号的xi，并且当出现错误并且信号f（x）与编码字f（xi）不匹配时，解码器7校正误差并输出xi，其中 被推断为原始信号。

公开(公告)号：US06223273B1

公开(公告)日：2001-04-24

申请号：US09271448

申请日：1999-03-18

申请人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

发明人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

IPC分类号： H01L2328

CPC分类号： H01L24/49 ,  G11C5/04 ,  G11C5/06 ,  H01L23/50 ,  H01L23/538 ,  H01L23/5386 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15183 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.

摘要翻译： 一种具有布线基板，至少两个半导体芯片和总线的电子电路封装。 通过总线连接的所有半导体芯片都是裸线封装在布线基板上，并且半导体芯片和布线基板通过在半导体芯片上形成的引线键合焊盘和布线基板之间的布线接合来连接。 布线基板可以是多层基板。 优选地，在多层布线基板的表面上形成绝缘层和形成在绝缘层的表面上的管芯接合接地，以便在芯片接合地下使用多层布线基板的一部分作为布线 或通孔区域，并且在芯片接合地上形成至少一个半导体芯片。 总线优选地包括两条数据总线，与一条数据总线连接的半导体芯片形成在布线基板的一侧，并且在另一条数据总线上连接的半导体芯片形成在布线基板的另一侧。

公开(公告)号：US06195742B1

公开(公告)日：2001-02-27

申请号：US09095049

申请日：1998-06-10

申请人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

发明人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

IPC分类号： G06F1300

CPC分类号： H01L24/49 ,  G11C5/04 ,  G11C5/06 ,  H01L23/50 ,  H01L23/538 ,  H01L23/5386 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15183 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.

摘要翻译： 一种具有布线基板，至少两个半导体芯片和总线的电子电路封装。 通过总线连接的所有半导体芯片都是裸线封装在布线基板上，并且半导体芯片和布线基板通过在半导体芯片上形成的引线键合焊盘和布线基板之间的布线接合来连接。 布线基板可以是多层基板。 优选地，在多层布线基板的表面上形成绝缘层和形成在绝缘层的表面上的管芯接合接地，以便在芯片接合地下使用多层布线基板的一部分作为布线 或通孔区域，并且在芯片接合地上形成至少一个半导体芯片。 总线优选地包括两条数据总线，与一条数据总线连接的半导体芯片形成在布线基板的一侧，并且在另一条数据总线上连接的半导体芯片形成在布线基板的另一侧。

公开(公告)号：US5848238A

公开(公告)日：1998-12-08

申请号：US778685

申请日：1997-01-03

申请人： Tetsuya Shimomura ,  Fumio Murabayashi ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Takashi Hotta

发明人： Tetsuya Shimomura ,  Fumio Murabayashi ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Takashi Hotta

IPC分类号： G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F11/22 ,  G06F11/30 ,  G06F13/00 ,  G06F15/78

CPC分类号： G06F11/1637 ,  G06F11/1654 ,  G06F11/2025 ,  G06F11/2038 ,  G06F11/2043

摘要： An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.

公开(公告)号：US09367438B2

公开(公告)日：2016-06-14

申请号：US14110786

申请日：2011-04-21

申请人： Hiromichi Yamada ,  Nobuyasu Kanekawa ,  Teruaki Sakata ,  Kesami Hagiwara ,  Yuichi Ishiguro

发明人： Hiromichi Yamada ,  Nobuyasu Kanekawa ,  Teruaki Sakata ,  Kesami Hagiwara ,  Yuichi Ishiguro

IPC分类号： G06F12/02 ,  G06F11/16

CPC分类号： G06F12/02 ,  G06F11/1641 ,  G06F11/167 ,  G06F11/1687 ,  G06F2201/845

摘要： First data to be written which is output from a function module (2) is supplied to a built-in memory (3) and a first buffer memory (11), and second data to be written which is output from the function module (2) is supplied to the built-in memory (3) and a second buffer memory (12). The first and second FIFO memories (13, 14) select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (11, 12), and do not select other data items. A comparator (15) compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories (13, 14) with each other.

摘要翻译： 从功能模块（2）输出的要写入的第一数据被提供给内置存储器（3）和第一缓冲存储器（11），以及从功能模块（2）输出的要写入的第二数据 ）被提供给内置存储器（3）和第二缓冲存储器（12）。 第一和第二FIFO存储器（13,14）从从第一和第二缓冲存储器（11,12）顺次输出的多个第一和第二输出数据项中选择并存储具有预定数量的输出的数据项，以及 不要选择其他数据项。 比较器（15）将由第一和第二FIFO存储器（13,14）输出的具有预定数量的输出的数据项彼此进行比较。

公开(公告)号：US09170587B2

公开(公告)日：2015-10-27

申请号：US13818107

申请日：2011-08-01

申请人： Teppei Hirotsu ,  Nobuyasu Kanekawa ,  Itaru Tanabe

发明人： Teppei Hirotsu ,  Nobuyasu Kanekawa ,  Itaru Tanabe

IPC分类号： G05F1/46 ,  G05F1/10 ,  H02P3/22 ,  H02P6/24

CPC分类号： G05F1/10 ,  H02P3/22 ,  H02P6/24

摘要： This invention provides a current control semiconductor element that can detect a current with high accuracy in a single IC chip by dynamically correcting changes in a gain a and an offset b, and a control device that uses the current control semiconductor element, the current control semiconductor element has a transistor 4, a current-to-voltage conversion circuit 22 and an AD converter 23 on the same semiconductor chip. A reference current generation circuit 6 superimposes a current pulse Ic on a current of a load 2 and changes a voltage digital value to be output from the AD converter. A gain/offset corrector 8 executes signal processing on change in the voltage digital value caused by the reference current generation circuit 6 to dynamically acquire the gain a and the offset b that are used in an equation that indicates a linear relationship between the voltage digital value output from the AD converter 23 and the current digital value of the load. A current digital value calculator 12 uses the gain and the offset acquired by the gain/offset corrector 8 to correct the voltage value output from the AD converter.

摘要翻译： 本发明提供了一种电流控制半导体元件，其可以通过动态地校正增益a和偏移b的变化，以及使用电流控制半导体元件的控制装置，电流控制半导体，可以在单个IC芯片中以高精度检测电流 元件在相同的半导体芯片上具有晶体管4，电流 - 电压转换电路22和AD转换器23。 参考电流产生电路6将电流脉冲Ic叠加在负载2的电流上，并改变要从AD转换器输出的电压数字值。 增益/偏移校正器8对由参考电流产生电路6引起的电压数字值的变化执行信号处理，以动态地获取在表示电压数字值之间的线性关系的方程式中使用的增益a和偏移量b AD转换器23的输出和负载的当前数字值。 当前数字值计算器12使用由增益/偏移校正器8获取的增益和偏移来校正从AD转换器输出的电压值。

公开(公告)号：US20130147453A1

公开(公告)日：2013-06-13

申请号：US13818107

申请日：2011-08-01

申请人： Teppei Hirotsu ,  Nobuyasu Kanekawa ,  Itaru Tanabe

发明人： Teppei Hirotsu ,  Nobuyasu Kanekawa ,  Itaru Tanabe

IPC分类号： G05F1/10

CPC分类号： G05F1/10 ,  H02P3/22 ,  H02P6/24

摘要： This invention provides a current control semiconductor element that can detect a current with high accuracy in a single IC chip by dynamically correcting changes in a gain a and an offset b, and a control device that uses the current control semiconductor element.The current control semiconductor element has a transistor 4, a current-to-voltage conversion circuit 22 and an AD converter 23 on the same semiconductor chip. A reference current generation circuit 6 superimposes a current pulse Ic on a current of a load 2 and changes a voltage digital value to be output from the AD converter. A gain/offset corrector 8 executes signal processing on change in the voltage digital value caused by the reference current generation circuit 6 to dynamically acquire the gain a and the offset b that are used in an equation that indicates a linear relationship between the voltage digital value output from the AD converter 23 and the current digital value of the load. A current digital value calculator 12 uses the gain and the offset acquired by the gain/offset corrector 8 to correct the voltage value output from the AD converter.

摘要翻译： 本发明提供一种电流控制半导体元件，其通过动态地校正增益a和偏移量b的变化，以及使用电流控制半导体元件的控制装置，可以在单个IC芯片中以高精度检测电流。 电流控制半导体元件在相同的半导体芯片上具有晶体管4，电流 - 电压转换电路22和AD转换器23。 参考电流产生电路6将电流脉冲Ic叠加在负载2的电流上，并改变要从AD转换器输出的电压数字值。 增益/偏移校正器8对由参考电流产生电路6引起的电压数字值的变化执行信号处理，以动态地获取在表示电压数字值之间的线性关系的方程式中使用的增益a和偏移量b AD转换器23的输出和负载的当前数字值。 当前数字值计算器12使用由增益/偏移校正器8获取的增益和偏移来校正从AD转换器输出的电压值。

公开(公告)号：US20130020978A1

公开(公告)日：2013-01-24

申请号：US13555123

申请日：2012-07-21

申请人： Hiromichi YAMADA ,  Teruaki Sakata ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro ,  Takashi Yasumasu ,  Kazuyoshi Fukuda ,  Kesami Hagiwara

发明人： Hiromichi YAMADA ,  Teruaki Sakata ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro ,  Takashi Yasumasu ,  Kazuyoshi Fukuda ,  Kesami Hagiwara

IPC分类号： H02P7/29 ,  G05B9/02

CPC分类号： G06F11/0754 ,  G06F11/0739 ,  G06F13/00 ,  Y02D10/14

摘要： A microcontroller includes a central processing unit, a PWM signal generation unit which generates a PWM signal according to a generation condition of a PWM signal set by the central processing unit, and a diagnostic unit which inputs the generated PWM signal therein and detects a pulse period and a pulse width, based on the input signal and which determines whether the detected pulse period and pulse width respectively coincide with a pulse period and a pulse width corresponding to the generation condition.

摘要翻译： 微控制器包括中央处理单元，根据由中央处理单元设置的PWM信号的生成条件产生PWM信号的PWM信号生成单元，以及在其中输入生成的PWM信号并检测脉冲周期的诊断单元 以及基于输入信号的脉冲宽度，并且确定检测到的脉冲周期和脉冲宽度是否与脉冲周期和对应于生成条件的脉冲宽度一致。

公开(公告)号：US08089233B2

公开(公告)日：2012-01-03

申请号：US12199367

申请日：2008-08-27

申请人： Nobuyasu Kanekawa ,  Masamichi Yamada ,  Shoji Sasaki ,  Katsuaki Fukatsu ,  Kenji Nakabayashi ,  Daisuke Terada

发明人： Nobuyasu Kanekawa ,  Masamichi Yamada ,  Shoji Sasaki ,  Katsuaki Fukatsu ,  Kenji Nakabayashi ,  Daisuke Terada

IPC分类号： H02K29/08

CPC分类号： G01D5/14

摘要： A first sensor element outputs a first output signal in correspondence to a direction of the magnetic flux lines acting from the outside. A second sensor element outputs a second output signal associated with the first output signal in correspondence to a direction of the magnetic flux lines acting from the outside. A first conversion processing section converts the first output signal output from the first sensor element and the second output signal output from the second sensor element into the second physical quantity. A second conversion processing section converts the first output signal output from the first sensor element and the second output signal output from the second sensor element into a signal representing the rotation angle of the motor.

摘要翻译： 第一传感器元件对应于从外部作用的磁通线的方向输出第一输出信号。 第二传感器元件对应于从外部作用的磁通线的方向输出与第一输出信号相关联的第二输出信号。 第一转换处理部将从第一传感器元件输出的第一输出信号和从第二传感器元件输出的第二输出信号转换为第二物理量。 第二转换处理部将从第一传感器元件输出的第一输出信号和从第二传感器元件输出的第二输出信号转换成表示电动机的旋转角度的信号。

公开(公告)号：US08046137B2

公开(公告)日：2011-10-25

申请号：US13004414

申请日：2011-01-11

申请人： Hiromichi Yamada ,  Nobuyasu Kanekawa ,  Teruaki Sakata

发明人： Hiromichi Yamada ,  Nobuyasu Kanekawa ,  Teruaki Sakata

IPC分类号： G06F17/00 ,  G06F17/50 ,  G06F1/04 ,  G06F11/00

CPC分类号： G06F11/1641 ,  G06F11/1679 ,  Y02T10/82

摘要： Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.

摘要翻译： 提供具有相同功能的两个数据处理单元，其中一个用于主机，另一个用于比较，电机单元的控制由主机执行，主数据处理单元和电路单元同步操作 利用第一时钟信号，第二数据处理单元与具有与第一时钟信号相同的周期和不同相位的第二时钟信号同步地操作，并且在比较电路中比较两个数据处理单元的处理结果。 触发器设置在从电路单元到比较数据处理单元和从主数据处理单元到比较器的信号路径的信号路径上，并且第一和第二时钟信号都用于触发器的锁存时钟 根据其输入信号。