公开(公告)号：US07701743B2

公开(公告)日：2010-04-20

申请号：US12222329

申请日：2008-08-07

申请人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

发明人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

IPC分类号： G11C5/06

CPC分类号： H01L24/49 ,  G11C5/04 ,  G11C5/06 ,  H01L23/50 ,  H01L23/538 ,  H01L23/5386 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15183 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor.

摘要翻译： 一种电子设备，其包括布线基板和布线基板上形成的多个半导体裸芯片。 半导体裸芯片包括用于处理数据的处理器和具有用于检测处理器的故障的检查功能的电路。

公开(公告)号：US07425763B2

公开(公告)日：2008-09-16

申请号：US11714747

申请日：2007-03-07

申请人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

发明人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

IPC分类号： H01L23/28

CPC分类号： H01L24/49 ,  G11C5/04 ,  G11C5/06 ,  H01L23/50 ,  H01L23/538 ,  H01L23/5386 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15183 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor.

摘要翻译： 一种电子设备，其包括布线基板和布线基板上形成的多个半导体裸芯片。 半导体裸芯片包括用于处理数据的处理器和具有用于检测处理器的故障的检查功能的电路。

公开(公告)号：US20070158814A1

公开(公告)日：2007-07-12

申请号：US11714747

申请日：2007-03-07

申请人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

发明人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L24/49 ,  G11C5/04 ,  G11C5/06 ,  H01L23/50 ,  H01L23/538 ,  H01L23/5386 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15183 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor

摘要翻译： 一种电子设备，其包括布线基板和布线基板上形成的多个半导体裸芯片。 半导体裸芯片包括用于处理数据的处理器和具有用于检测处理器的故障的检查功能的电路

公开(公告)号：US5789805A

公开(公告)日：1998-08-04

申请号：US746942

申请日：1996-11-18

申请人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

发明人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

IPC分类号： G06F1/18 ,  G06F3/00 ,  G06F11/10 ,  G06F11/22 ,  G06F12/16 ,  G06F15/78 ,  G11C5/00 ,  H01L23/495 ,  H01L23/50 ,  H01L23/538 ,  H01L25/04 ,  H01L25/065 ,  H01L25/18 ,  H01L23/28

CPC分类号： H01L24/49 ,  G11C5/04 ,  G11C5/06 ,  H01L23/50 ,  H01L23/538 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15183 ,  H01L2924/15787

摘要： An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the is surface of the insulating layer, in order to use a portion of the multilayer wing substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.

摘要翻译： 一种具有布线基板，至少两个半导体芯片和总线的电子电路封装。 通过总线连接的所有半导体芯片都是裸线封装在布线基板上，并且半导体芯片和布线基板通过在半导体芯片上形成的引线键合焊盘和布线基板之间的布线接合来连接。 布线基板可以是多层。 优选地，在多层布线基板的表面上部分地形成有绝缘层和形成在绝缘层的表面上的芯片接合接地，以便在芯片接合地下使用多层翼基板的一部分作为 布线或通孔区域，并且在芯片接合地上形成至少一个半导体芯片。 总线优选地包括两条数据总线，与一条数据总线连接的半导体芯片形成在布线基板的一侧，并且在另一条数据总线上连接的半导体芯片形成在布线基板的另一侧。

公开(公告)号：US5614761A

公开(公告)日：1997-03-25

申请号：US523346

申请日：1995-09-05

申请人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

发明人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

IPC分类号： G06F1/18 ,  G06F3/00 ,  G06F11/10 ,  G06F11/22 ,  G06F12/16 ,  G06F15/78 ,  G11C5/00 ,  H01L23/495 ,  H01L23/50 ,  H01L23/538 ,  H01L25/04 ,  H01L25/065 ,  H01L25/18 ,  H01L23/28

CPC分类号： H01L24/49 ,  G11C5/04 ,  G11C5/06 ,  H01L23/50 ,  H01L23/538 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15183 ,  H01L2924/15787

摘要： An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.

摘要翻译： 一种具有布线基板，至少两个半导体芯片和总线的电子电路封装。 通过总线连接的所有半导体芯片都是裸线封装在布线基板上，并且半导体芯片和布线基板通过在半导体芯片上形成的引线键合焊盘和布线基板之间的布线接合来连接。 布线基板可以是多层基板。 优选地，在多层布线基板的表面上形成绝缘层和形成在绝缘层的表面上的管芯接合接地，以便在芯片接合地下使用多层布线基板的一部分作为布线 或通孔区域，并且在芯片接合地上形成至少一个半导体芯片。 总线优选地包括两条数据总线，与一条数据总线连接的半导体芯片形成在布线基板的一侧，并且在另一条数据总线上连接的半导体芯片形成在布线基板的另一侧。

公开(公告)号：US5468992A

公开(公告)日：1995-11-21

申请号：US843234

申请日：1992-02-28

申请人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

发明人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

IPC分类号： G06F1/18 ,  G06F3/00 ,  G06F11/10 ,  G06F11/22 ,  G06F12/16 ,  G06F15/78 ,  G11C5/00 ,  H01L23/495 ,  H01L23/50 ,  H01L23/538 ,  H01L25/04 ,  H01L25/065 ,  H01L25/18 ,  H01L23/28 ,  H01L27/04 ,  H05K3/10

CPC分类号： H01L24/49 ,  G11C5/04 ,  G11C5/06 ,  H01L23/50 ,  H01L23/538 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15183 ,  H01L2924/15787

摘要： An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wire bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer element. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, thereby making it possible to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line being formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line being formed on the other side of the wiring substrate.

摘要翻译： 一种具有布线基板，至少两个半导体芯片和总线的电子电路封装。 通过总线连接的所有半导体芯片都是裸线封装在布线基板上，并且半导体芯片和布线基板通过在半导体芯片和布线基板之间形成的引线键合焊盘之间的引线接合来连接。 布线基板可以是多层元件。 优选地，在多层布线基板的表面上形成有绝缘层和形成在绝缘层的表面上的管芯接合接地，从而可以将芯片接合地下的多层布线基板的一部分作为 布线或通孔区域，并且在芯片接合地上形成至少一个半导体芯片。 总线线路优选地包括两条数据总线，与布线基板的一侧上形成的一条数据总线相连的半导体芯片和与另一数据总线相连的半导体芯片形成在布线基板的另一侧。

公开(公告)号：US08269295B2

公开(公告)日：2012-09-18

申请号：US13088725

申请日：2011-04-18

申请人： Takashi Takenaga ,  Takeharu Kuroiwa ,  Hiroshi Takada ,  Shuichi Ueno ,  Kiyoshi Kawabata

发明人： Takashi Takenaga ,  Takeharu Kuroiwa ,  Hiroshi Takada ,  Shuichi Ueno ,  Kiyoshi Kawabata

IPC分类号： H01L29/82 ,  G11C11/02

CPC分类号： H01L27/228 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L43/08

摘要： There is provided a magnetic memory device stable in write characteristics. The magnetic memory device has a recording layer. The planar shape of the recording layer has the maximum length in the direction of the easy-axis over a primary straight line along the easy-axis, and is situated over a length smaller than the half of the maximum length in the direction perpendicular to the easy-axis, and on the one side and on the other side of the primary straight line respectively, the planar shape has a first part situated over a length in the direction perpendicular to the easy-axis, and a second part situated over a length smaller than the length in the direction perpendicular to the easy-axis. The outer edge of the first part includes only a smooth curve convex outwardly of the outer edge.

摘要翻译： 提供了一种写入特性稳定的磁存储器件。 磁存储器件具有记录层。 记录层的平面形状沿着容易轴在易于轴的方向上在主直线上具有最大长度，并且位于比垂直于该方向的方向上的最大长度的一半长度 分别在主直线的一侧和另一侧上，平面形状具有位于垂直于易轴的方向上的长度的第一部分，以及位于长度方向上的第二部分 小于垂直于易轴方向的长度。 第一部分的外边缘仅包括从外边缘向外凸出的平滑曲线。

公开(公告)号：US20110193185A1

公开(公告)日：2011-08-11

申请号：US13088725

申请日：2011-04-18

申请人： Takashi Takenaga ,  Takeharu Kuroiwa ,  Hiroshi Takada ,  Shuichi Ueno ,  Kiyoshi Kawabata

发明人： Takashi Takenaga ,  Takeharu Kuroiwa ,  Hiroshi Takada ,  Shuichi Ueno ,  Kiyoshi Kawabata

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L43/08

摘要： There is provided a magnetic memory device stable in write characteristics. The magnetic memory device has a recording layer. The planar shape of the recording layer has the maximum length in the direction of the easy-axis over a primary straight line along the easy-axis, and is situated over a length smaller than the half of the maximum length in the direction perpendicular to the easy-axis, and on the one side and on the other side of the primary straight line respectively, the planar shape has a first part situated over a length in the direction perpendicular to the easy-axis, and a second part situated over a length smaller than the length in the direction perpendicular to the easy-axis. The outer edge of the first part includes only a smooth curve convex outwardly of the outer edge.

摘要翻译： 提供了一种写入特性稳定的磁存储器件。 磁存储器件具有记录层。 记录层的平面形状沿着容易轴在易于轴的方向上在主直线上具有最大长度，并且位于比垂直于该方向的方向上的最大长度的一半长度 分别在主直线的一侧和另一侧上，平面形状具有位于垂直于易轴的方向上的长度的第一部分，以及位于长度方向上的第二部分 小于垂直于易轴方向的长度。 第一部分的外边缘仅包括从外边缘向外凸出的平滑曲线。

公开(公告)号：US06584004B2

公开(公告)日：2003-06-24

申请号：US09793968

申请日：2001-02-28

申请人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

发明人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

IPC分类号： H01L2328

CPC分类号： H01L24/49 ,  G11C5/04 ,  G11C5/06 ,  H01L23/50 ,  H01L23/538 ,  H01L23/5386 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15183 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.

公开(公告)号：US4386387A

公开(公告)日：1983-05-31

申请号：US321609

申请日：1981-11-16

申请人： Hirayoshi Tanei ,  Akira Ikegami ,  Hideo Arima ,  Tokio Isogai ,  Kiyoshi Kawabata

发明人： Hirayoshi Tanei ,  Akira Ikegami ,  Hideo Arima ,  Tokio Isogai ,  Kiyoshi Kawabata

IPC分类号： C04B35/00 ,  C04B35/499 ,  H01G4/12 ,  C04B35/46

CPC分类号： H01G4/1263 ,  C04B35/499

摘要： A porcelain composition comprising Pb(Fe.sub.2/3 W.sub.1/3)O.sub.3, PbTiO.sub.3 and Pb(Yb.sub.1/2 Nb.sub.1/2)O.sub.3 preferably within the range as defined by closed area of A-B-C-D-A in the accompanying triangular diagram can give a sintered product by sintering at a temperature as low as 1000.degree. C. or lower. The resulting sintered product has a high relative dielectric constant and a small dielectric loss tangent.

摘要翻译： 包含Pb（Fe2 / 3W1 / 3）O3，PbTiO3和Pb（Yb1 / 2Nb1 / 2）O3的瓷组合物优选在由三角形图中的ABCDA的封闭区域限定的范围内，可以通过在 温度低至1000℃或更低。 所得到的烧结产品具有高的相对介电常数和小的介电损耗角正切。