公开(公告)号：US20090153897A1

公开(公告)日：2009-06-18

申请号：US11958668

申请日：2007-12-18

申请人： Robert S. Blackmore ,  Ramakrishnan Rajamony

发明人： Robert S. Blackmore ,  Ramakrishnan Rajamony

IPC分类号： G06F3/12

CPC分类号： G06F9/5016 ,  G06F12/0284 ,  G06F12/109 ,  G06F2212/656

摘要： A method of operating a data processing system includes each of multiple tasks within a parallel job executing on multiple nodes of the data processing system issuing a respective system call to request reservation, without allocation of backing storage in physical memory, of a global address space defined by a range of effective addresses as global shared memory accessible to all of the multiple tasks within the parallel job. At least two of the tasks within the parallel job allocate global address spaces including a same effective address.

摘要翻译： 一种操作数据处理系统的方法包括在数据处理系统的多个节点上执行的并行作业中的每个，发出相应的系统调用以请求预留，而不在物理存储器中分配备份存储器，以定义全局地址空间 通过一系列有效地址作为并行作业内的所有多个任务可访问的全局共享内存。 并行作业中的至少两个任务分配全局地址空间，包括相同的有效地址。

公开(公告)号：US07925842B2

公开(公告)日：2011-04-12

申请号：US11958956

申请日：2007-12-18

申请人： Ravi K. Arimilli ,  Robert S. Blackmore ,  Ramakrishnan Rajamony ,  William J. Starke

发明人： Ravi K. Arimilli ,  Robert S. Blackmore ,  Ramakrishnan Rajamony ,  William J. Starke

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0284 ,  G06F2212/1048

摘要： A method of operating a data processing system includes each of multiple tasks within a parallel job executing on multiple nodes of the data processing system issuing a system call to request allocation of backing storage in physical memory for global shared memory accessible to all of the multiple tasks within the parallel job, where the global shared memory is in a global address space defined by a range of effective addresses. Each task among the multiple tasks receives an indication that the allocation requested by the system call was successful only if the global address space for that task was previously reserved and backing storage for the global shared memory has not already been allocated.

摘要翻译： 一种操作数据处理系统的方法包括执行在数据处理系统的多个节点上的并行作业中的多个任务中的每个，发出系统调用以请求在物理存储器中分配后备存储器，用于所有多个任务可访问的全局共享存储器 在并行作业中，全局共享存储器位于由一系列有效地址定义的全局地址空间中。 多个任务之间的每个任务都接收到一个指示，即仅当该任务的全局地址空间以前被保留并且尚未分配全局共享存储器的备份存储时，系统调用所请求的分配才成功。

公开(公告)号：US20090157996A1

公开(公告)日：2009-06-18

申请号：US11958956

申请日：2007-12-18

申请人： Ravi K. Arimilli ,  Robert S. Blackmore ,  Ramakrishnan Rajamony ,  William J. Starke

发明人： Ravi K. Arimilli ,  Robert S. Blackmore ,  Ramakrishnan Rajamony ,  William J. Starke

IPC分类号： G06F12/02

CPC分类号： G06F12/0284 ,  G06F2212/1048

摘要： A method of operating a data processing system includes each of multiple tasks within a parallel job executing on multiple nodes of the data processing system issuing a system call to request allocation of backing storage in physical memory for global shared memory accessible to all of the multiple tasks within the parallel job, where the global shared memory is in a global address space defined by a range of effective addresses. Each task among the multiple tasks receives an indication that the allocation requested by the system call was successful only if the global address space for that task was previously reserved and backing storage for the global shared memory has not already been allocated.

摘要翻译： 一种操作数据处理系统的方法包括执行在数据处理系统的多个节点上的并行作业中的多个任务中的每个，发出系统调用以请求在物理存储器中分配后备存储器，用于所有多个任务可访问的全局共享存储器 在并行作业中，全局共享存储器位于由一系列有效地址定义的全局地址空间中。 多个任务之间的每个任务都接收到一个指示，即仅当该任务的全局地址空间以前被保留并且尚未分配全局共享存储器的备份存储时，系统调用所请求的分配才成功。

公开(公告)号：US07966454B2

公开(公告)日：2011-06-21

申请号：US12024437

申请日：2008-02-01

申请人： Lakshimarayana B. Arimilli ,  Ravi K. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Ramakrishnan Rajamony ,  William J. Starke ,  Hanhong Xue

发明人： Lakshimarayana B. Arimilli ,  Ravi K. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Ramakrishnan Rajamony ,  William J. Starke ,  Hanhong Xue

IPC分类号： G06F9/318

CPC分类号： G06F12/0815 ,  G06F12/0897 ,  G06F12/10

摘要： A data processing system enables global shared memory (GSM) operations across multiple nodes with a distributed EA-to-RA mapping of physical memory. Each node has a host fabric interface (HFI), which includes HFI windows that are assigned to at most one locally-executing task of a parallel job. The tasks perform parallel job execution, but map only a portion of the effective addresses (EAs) of the global address space to the local, real memory of the task's respective node. The HFI window tags all outgoing GSM operations (of the local task) with the job ID, and embeds the target node and HFI window IDs of the node at which the EA is memory mapped. The HFI window also enables processing of received GSM operations with valid EAs that are homed to the local real memory of the receiving node, while preventing processing of other received operations without a valid EA-to-RA local mapping.

摘要翻译： 数据处理系统通过物理内存的分布式EA-to-RA映射实现跨多个节点的全局共享存储（GSM）操作。 每个节点都有一个主机结构接口（HFI），它包括分配给并行作业最多一个本地执行任务的HFI窗口。 任务执行并行作业执行，但将全局地址空间的有效地址（EA）的一部分映射到任务相应节点的本地实际存储器。 HFI窗口使用作业ID对所有传出的GSM操作（本地任务）进行标记，并嵌入EA被映射到的节点的目标节点和HFI窗口ID。 HFI窗口还能够利用归属于接收节点的本地实际存储器的有效EA来处理接收的GSM操作，同时防止在没有有效的EA到RA本地映射的情况下处理其他接收到的操作。

公开(公告)号：US08966219B2

公开(公告)日：2015-02-24

申请号：US11928125

申请日：2007-10-30

申请人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

发明人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/10

CPC分类号： G06F12/1063 ,  G06F12/1072

摘要： In a data processing system capable of concurrently executing multiple hardware threads of execution, an intermediate address translation unit in a processing unit translates an effective address for a memory access into an intermediate address. A cache memory is accessed utilizing the intermediate address. In response to a miss in cache memory, the intermediate address is translated into a real address by a real address translation unit that performs address translation for multiple hardware threads of execution. The system memory is accessed with the real address.

摘要翻译： 在能够同时执行多个硬件执行线程的数据处理系统中，处理单元中的中间地址转换单元将存储器访问的有效地址转换为中间地址。 使用中间地址访问高速缓冲存储器。 响应于高速缓冲存储器中的缺失，中间地址被实现地址转换单元转换成实地址，该单元执行多个硬件执行线程的地址转换。 使用实际地址访问系统内存。

公开(公告)号：US08843705B2

公开(公告)日：2014-09-23

申请号：US13572916

申请日：2012-08-13

申请人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

发明人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/08

CPC分类号： G06F12/0848 ,  G06F2212/271 ,  Y02D10/13

摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.

摘要翻译： 在缓存中提供了一种机制，用于提供读写感知高速缓存。 该机制将大型缓存分区分为常读区域和经常写区域。 该机制将读/写频率视为非均匀缓存架构替换策略。 经常写入的高速缓存行放置在更远的存储区之一中。 经常读取的高速缓存行被放置在其中一个较近的存储体中。 常读区域和经常写区域之间的大小比可以是静态的或动态的。 经常读区域和经常写区域之间的边界可能是不同的或模糊的。

公开(公告)号：US20120198459A1

公开(公告)日：2012-08-02

申请号：US13434423

申请日：2012-03-29

申请人： Patrick Joseph Bohrer ,  Orran Yaakov Krieger ,  Ramakrishnan Rajamony ,  Michael Rosenfield ,  Hazim Shafi ,  Balaram Sinharoy ,  Robert Brett Tremaine

发明人： Patrick Joseph Bohrer ,  Orran Yaakov Krieger ,  Ramakrishnan Rajamony ,  Michael Rosenfield ,  Hazim Shafi ,  Balaram Sinharoy ,  Robert Brett Tremaine

IPC分类号： G06F9/46 ,  G06F12/08

CPC分类号： G06F9/383 ,  G06F9/3851 ,  G06F9/4881 ,  G06F12/0862

摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.

摘要翻译： 数据处理系统包括具有访问多级缓存存储器的微处理器。 微处理器执行从源代码对象编译的主线程。 该系统包括用于执行也源自源代码对象的辅助线程的处理器。 辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。 配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。 辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

公开(公告)号：US20120195591A1

公开(公告)日：2012-08-02

申请号：US13444762

申请日：2012-04-11

申请人： Alan Benner ,  Ramakrishnan Rajamony ,  Eugen Schenfeld ,  Craig Brian Stunkel ,  Peter A. Walker

发明人： Alan Benner ,  Ramakrishnan Rajamony ,  Eugen Schenfeld ,  Craig Brian Stunkel ,  Peter A. Walker

IPC分类号： H04L12/66 ,  H04J14/00

CPC分类号： H04L12/4641 ,  H04L12/28 ,  H04L12/66

摘要： A computing system includes: a plurality of tightly coupled processing nodes; a plurality of circuit switched networks using a circuit switching mode, interconnecting the processing nodes, and handling data transfers that meet one or more criteria; and a plurality of electronic packet switched networks, also interconnecting the processing nodes, handling data transfers that do meet the at least one criteria. The circuit switched networks and the electronic packet switched networks operate simultaneously.

摘要翻译： 计算系统包括：多个紧密耦合的处理节点; 使用电路交换模式的多个电路交换网络，互连处理节点，以及处理满足一个或多个标准的数据传输; 以及多个电子分组交换网络，其还互连处理节点，处理满足至少一个准则的数据传输。 电路交换网络和电子分组交换网络同时工作。

公开(公告)号：US08230422B2

公开(公告)日：2012-07-24

申请号：US11034546

申请日：2005-01-13

申请人： Patrick Joseph Bohrer ,  Orran Yaakov Krieger ,  Ramakrishnan Rajamony ,  Michael Rosenfield ,  Hazim Shafi ,  Balaram Sinharoy ,  Robert Brett Tremaine

发明人： Patrick Joseph Bohrer ,  Orran Yaakov Krieger ,  Ramakrishnan Rajamony ,  Michael Rosenfield ,  Hazim Shafi ,  Balaram Sinharoy ,  Robert Brett Tremaine

IPC分类号： G06F9/46 ,  G06F9/40 ,  G06F13/28

CPC分类号： G06F9/383 ,  G06F9/3851 ,  G06F9/4881 ,  G06F12/0862

摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.

摘要翻译： 数据处理系统包括具有访问多级缓存存储器的微处理器。 微处理器执行从源代码对象编译的主线程。 该系统包括用于执行也源自源代码对象的辅助线程的处理器。 辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。 配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。 辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

公开(公告)号：US08140759B2

公开(公告)日：2012-03-20

申请号：US12424716

申请日：2009-04-16

申请人： Bradly George Frey ,  Guy Lynn Guthrie ,  Cathy May ,  Ramakrishnan Rajamony ,  Balaram Sinharoy ,  William John Starke ,  Peter Kenneth Szwed

发明人： Bradly George Frey ,  Guy Lynn Guthrie ,  Cathy May ,  Ramakrishnan Rajamony ,  Balaram Sinharoy ,  William John Starke ,  Peter Kenneth Szwed

IPC分类号： G06F13/00

CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0817 ,  G06F2212/6028

摘要： A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.

摘要翻译： 用于指定用于仅预取高速缓存块数据的子部分的访问提示的系统和方法，用于处理器核心的更有效的系统互连使用。 处理单元接收包含访问提示的数据高速缓存块触摸（DCBT）指令，并且识别要预取的数据的特定大小部分。 访问提示和对应于要预取的数据量的值都包含在DCBT指令的单独子字段中。 响应于检测到代码点被设置为特定值，仅在DCBT指令的DCBT的子字段中标识的数据的特定大小被预取到低级缓存中的条目中。