公开(公告)号：US20120286341A1

公开(公告)日：2012-11-15

申请号：US13106521

申请日：2011-05-12

申请人： Kuo-Ji Chen ,  Li-Chun Tien

发明人： Kuo-Ji Chen ,  Li-Chun Tien

IPC分类号： H01L29/94

CPC分类号： H01L29/94 ,  H01L23/528 ,  H01L27/0805 ,  H01L27/0808 ,  H01L29/107 ,  H01L29/1095 ,  H01L2924/0002 ,  H01L2924/00

摘要： A tap cell includes a well region and a well pickup region on the well region; a VDD power rail; and a VSS power rail. A MOS capacitor includes a gate electrode line acting as a first capacitor plate, and the well pickup region acting as a part of a second capacitor plate. A first one of the first and second capacitor plates is coupled to the VDD power rail, and a second one of the first and second capacitor plates is coupled to the VSS power rail.

摘要翻译： 抽头单元包括阱区域和阱区域上的阱拾取区域; 一个VDD电源轨; 和VSS电源轨。 MOS电容器包括用作第一电容器板的栅极电极线和用作第二电容器板的一部分的阱拾取区域。 第一和第二电容器板中的第一电容器板耦合到VDD电源轨，并且第一和第二电容器板中的第二个耦合到VSS电源轨。

公开(公告)号：US20070284618A1

公开(公告)日：2007-12-13

申请号：US11441557

申请日：2006-05-26

申请人： Mi-Chang Chang ,  Liang-Kai Han ,  Huan-Tsung Huang ,  Wen-Jya Liang ,  Li-Chun Tien

发明人： Mi-Chang Chang ,  Liang-Kai Han ,  Huan-Tsung Huang ,  Wen-Jya Liang ,  Li-Chun Tien

IPC分类号： H01L27/10 ,  H01L29/739

CPC分类号： H01L27/0207 ,  H01L27/11803 ,  H01L29/7849

摘要： A layout for a transistor in a standard cell is disclosed. The layout for a transistor comprises an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.

摘要翻译： 公开了一种用于标准单元中晶体管的布局。 晶体管的布局包括有源区，其中至少一个部分具有第一边缘，并且至少一个部分具有全部垂直于该晶体管的沟道的第二边缘; 并且放置在有源区域的顶部上的栅极与栅极的边缘到第一边缘的距离短于距栅极的边缘到有源区域的第二边缘的距离，其中有源区域为 非矩形。

公开(公告)号：US20050086629A1

公开(公告)日：2005-04-21

申请号：US10688500

申请日：2003-10-17

申请人： Jaw-Jung Shin ,  Chun-Kuang Chen ,  Tsai-Sheng Gau ,  Burn-Jeng Lin ,  Li-Chun Tien ,  Mi-Chang Chang ,  Yu-Jun Chou ,  Jan-Wen You ,  King-Chang Shu ,  Li-Jui Chen

发明人： Jaw-Jung Shin ,  Chun-Kuang Chen ,  Tsai-Sheng Gau ,  Burn-Jeng Lin ,  Li-Chun Tien ,  Mi-Chang Chang ,  Yu-Jun Chou ,  Jan-Wen You ,  King-Chang Shu ,  Li-Jui Chen

IPC分类号： G03F1/14 ,  G03F7/20 ,  G06F17/50

CPC分类号： G03F7/70641 ,  G03F1/44 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/705

摘要： A method of identifying and defining forbidden pitches or forbidden pitch ranges for a lithographic exposure tool under a given set of exposure conditions is provided. In the method, a computer simulation is performed, and its results are compared to frequently used pitches to see if such frequently used pitches may yield depth-of-focus (DOF) values greater than the focus budget for the exposure tool. If so, a verification test is performed by using a test mask and actually exposing a surface with the same pattern pitches simulated. From this, actual DOF values are obtained and compared to the focus budget of the exposure tool. Any pitches having a DOF value greater than the focus budget are designated as forbidden pitches. This forbidden pitch information may be integrated into a design rule to restrict the use of such forbidden pitches under the given exposure conditions where they are likely to arise.

公开(公告)号：US08819610B2

公开(公告)日：2014-08-26

申请号：US13778912

申请日：2013-02-27

申请人： Hsiang-Jen Tseng ,  Ting-Wei Chiang ,  Wei-Yu Chen ,  Ruei-Wun Sun ,  Hung-Jung Tseng ,  Shun Li Chen ,  Li-Chun Tien

发明人： Hsiang-Jen Tseng ,  Ting-Wei Chiang ,  Wei-Yu Chen ,  Ruei-Wun Sun ,  Hung-Jung Tseng ,  Shun Li Chen ,  Li-Chun Tien

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5068 ,  G06F17/5072 ,  H01L23/4824 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit layout includes a P-type active region, an N-type active region, a first metal connection, a second metal connection and a plurality of trunks. The plurality of trunks is formed substantially side-by-side, and in parallel with each other. The first metal connection is substantially disposed over the P-type active region, and is electrically connected with drain regions of PMOS transistors in the P-type active region. The second metal connection is substantially disposed over the N-type active region, and is electrically connected with drain regions of NMOS transistors in the N-type active region. The plurality of trunks is electrically connected with and is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks and is arranged to be located between two groups of trunks.

摘要翻译： 集成电路布局包括P型有源区，N型有源区，第一金属连接，第二金属连接和多个树干。 多个树干基本并排地形成并且彼此平行。 第一金属连接基本上设置在P型有源区上，并且与P型有源区中的PMOS晶体管的漏极区域电连接。 第二金属连接基本上设置在N型有源区上，并且与N型有源区中的NMOS晶体管的漏区电连接。 多个树干电连接并且基本上垂直于第一金属连接和第二金属连接。 多个树干的第一树干具有比多个树干中的其他树干的宽度宽的宽度，并且布置成位于两组树干之间。

公开(公告)号：US08455354B2

公开(公告)日：2013-06-04

申请号：US13081115

申请日：2011-04-06

申请人： Jung-Hsuan Chen ,  Yen-Huei Chen ,  Li-Chun Tien ,  Hung-Jen Liao

发明人： Jung-Hsuan Chen ,  Yen-Huei Chen ,  Li-Chun Tien ,  Hung-Jen Liao

IPC分类号： H01L21/28

CPC分类号： H01L21/32139 ,  H01L21/76816

摘要： A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.

摘要翻译： 形成集成电路的方法包括在栅电极线上形成掩模层，其中栅电极线在半导体衬底的阱区之上; 在所述掩模层中形成开口，其中所述栅电极线的一部分和所述阱区的阱拾取区域通过所述开口露出; 并且通过所述开口去除所述栅电极线的所述部分。

公开(公告)号：US20130069236A1

公开(公告)日：2013-03-21

申请号：US13238294

申请日：2011-09-21

申请人： Jung-Hsuan Chen ,  May Chang ,  Chiting Cheng ,  Li-Chun Tien

发明人： Jung-Hsuan Chen ,  May Chang ,  Chiting Cheng ,  Li-Chun Tien

IPC分类号： H01L23/52 ,  G06F17/50

CPC分类号： H01L27/0207 ,  H01L2027/11859

摘要： Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.

摘要翻译： 提供半导体器件单元，用于形成半导体器件单元的方法和用于半导体器件单元的布局样式。 器件单元可以是整个集成电路中使用的重复单元。 布局样式利用多晶硅级别的无多晶硅的区域，并且其可以容纳其中或其中的导电引线。 导电引线由通常用于触点或通孔的材料形成，并且设置在将器件单元彼此耦合的第一金属互连级之下。 下面的局部导电引线可以形成下面的信号线，允许额外的功率网线被包括在可以容纳在器件单元内并根据金属轨道设计间隔规则的有限数量的金属轨道内。

公开(公告)号：US06973636B2

公开(公告)日：2005-12-06

申请号：US10688500

申请日：2003-10-17

申请人： Jaw-Jung Shin ,  Chun-Kuang Chen ,  Tsai-Sheng Gau ,  Burn-Jeng Lin ,  Li-Chun Tien ,  Mi-Chang Chang ,  Yu-Jun Chou ,  Jan-Wen You ,  King-Chang Shu ,  Li-Jui Chen

发明人： Jaw-Jung Shin ,  Chun-Kuang Chen ,  Tsai-Sheng Gau ,  Burn-Jeng Lin ,  Li-Chun Tien ,  Mi-Chang Chang ,  Yu-Jun Chou ,  Jan-Wen You ,  King-Chang Shu ,  Li-Jui Chen

IPC分类号： G03F1/14 ,  G03F7/20 ,  G06F17/50

CPC分类号： G03F7/70641 ,  G03F1/44 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/705

摘要： A method of identifying and defining forbidden pitches or forbidden pitch ranges for a lithographic exposure tool under a given set of exposure conditions is provided. In the method, a computer simulation is performed, and its results are compared to frequently used pitches to see if such frequently used pitches may yield depth-of-focus (DOF) values greater than the focus budget for the exposure tool. If so, a verification test is performed by using a test mask and actually exposing a surface with the same pattern pitches simulated. From this, actual DOF values are obtained and compared to the focus budget of the exposure tool. Any pitches having a DOF value greater than the focus budget are designated as forbidden pitches. This forbidden pitch information may be integrated into a design rule to restrict the use of such forbidden pitches under the given exposure conditions where they are likely to arise.

摘要翻译： 提供了一种在给定的曝光条件下识别和限定光刻曝光工具的禁止间距或禁止间距范围的方法。 在该方法中，执行计算机模拟，并将其结果与经常使用的间距进行比较，以查看这种经常使用的间距是否可以产生比曝光工具的焦点预算大的焦点深度（DOF）值。 如果是这样，则通过使用测试掩模执行验证测试，并且实际上暴露出模拟相同模式间距的表面。 从此，获得实际的DOF值，并与曝光工具的焦点预算进行比较。 DOF值大于焦点预算的任何间距都被指定为禁止间距。 该禁止音调信息可以被集成到设计规则中，以限制在可能出现的给定曝光条件下使用这种禁止间距。