公开(公告)号：US07321139B2

公开(公告)日：2008-01-22

申请号：US11441557

申请日：2006-05-26

申请人： Mi-Chang Chang ,  Liang-Kai Han ,  Huan-Tsung Huang ,  Wen-Jya Liang ,  Li-Chun Tien

发明人： Mi-Chang Chang ,  Liang-Kai Han ,  Huan-Tsung Huang ,  Wen-Jya Liang ,  Li-Chun Tien

IPC分类号： H01L27/10 ,  H01L29/739 ,  H01L29/73 ,  H01L29/74 ,  H01L31/062

CPC分类号： H01L27/0207 ,  H01L27/11803 ,  H01L29/7849

摘要： A layout for a transistor in a standard cell is disclosed. The layout for a transistor includes an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.

摘要翻译： 公开了一种用于标准单元中晶体管的布局。 晶体管的布局包括有源区，其中至少一个部分具有第一边缘，并且至少一个部分具有全部垂直于晶体管的沟道的第二边缘; 并且放置在有源区域的顶部上的栅极与栅极的边缘到第一边缘的距离短于距栅极的边缘到有源区域的第二边缘的距离，其中有源区域为 非矩形。

公开(公告)号：US20070284618A1

公开(公告)日：2007-12-13

申请号：US11441557

申请日：2006-05-26

申请人： Mi-Chang Chang ,  Liang-Kai Han ,  Huan-Tsung Huang ,  Wen-Jya Liang ,  Li-Chun Tien

发明人： Mi-Chang Chang ,  Liang-Kai Han ,  Huan-Tsung Huang ,  Wen-Jya Liang ,  Li-Chun Tien

IPC分类号： H01L27/10 ,  H01L29/739

CPC分类号： H01L27/0207 ,  H01L27/11803 ,  H01L29/7849

摘要： A layout for a transistor in a standard cell is disclosed. The layout for a transistor comprises an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.

摘要翻译： 公开了一种用于标准单元中晶体管的布局。 晶体管的布局包括有源区，其中至少一个部分具有第一边缘，并且至少一个部分具有全部垂直于该晶体管的沟道的第二边缘; 并且放置在有源区域的顶部上的栅极与栅极的边缘到第一边缘的距离短于距栅极的边缘到有源区域的第二边缘的距离，其中有源区域为 非矩形。

公开(公告)号：US20050086629A1

公开(公告)日：2005-04-21

申请号：US10688500

申请日：2003-10-17

申请人： Jaw-Jung Shin ,  Chun-Kuang Chen ,  Tsai-Sheng Gau ,  Burn-Jeng Lin ,  Li-Chun Tien ,  Mi-Chang Chang ,  Yu-Jun Chou ,  Jan-Wen You ,  King-Chang Shu ,  Li-Jui Chen

发明人： Jaw-Jung Shin ,  Chun-Kuang Chen ,  Tsai-Sheng Gau ,  Burn-Jeng Lin ,  Li-Chun Tien ,  Mi-Chang Chang ,  Yu-Jun Chou ,  Jan-Wen You ,  King-Chang Shu ,  Li-Jui Chen

IPC分类号： G03F1/14 ,  G03F7/20 ,  G06F17/50

CPC分类号： G03F7/70641 ,  G03F1/44 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/705

摘要： A method of identifying and defining forbidden pitches or forbidden pitch ranges for a lithographic exposure tool under a given set of exposure conditions is provided. In the method, a computer simulation is performed, and its results are compared to frequently used pitches to see if such frequently used pitches may yield depth-of-focus (DOF) values greater than the focus budget for the exposure tool. If so, a verification test is performed by using a test mask and actually exposing a surface with the same pattern pitches simulated. From this, actual DOF values are obtained and compared to the focus budget of the exposure tool. Any pitches having a DOF value greater than the focus budget are designated as forbidden pitches. This forbidden pitch information may be integrated into a design rule to restrict the use of such forbidden pitches under the given exposure conditions where they are likely to arise.

公开(公告)号：US06973636B2

公开(公告)日：2005-12-06

申请号：US10688500

申请日：2003-10-17

申请人： Jaw-Jung Shin ,  Chun-Kuang Chen ,  Tsai-Sheng Gau ,  Burn-Jeng Lin ,  Li-Chun Tien ,  Mi-Chang Chang ,  Yu-Jun Chou ,  Jan-Wen You ,  King-Chang Shu ,  Li-Jui Chen

发明人： Jaw-Jung Shin ,  Chun-Kuang Chen ,  Tsai-Sheng Gau ,  Burn-Jeng Lin ,  Li-Chun Tien ,  Mi-Chang Chang ,  Yu-Jun Chou ,  Jan-Wen You ,  King-Chang Shu ,  Li-Jui Chen

IPC分类号： G03F1/14 ,  G03F7/20 ,  G06F17/50

CPC分类号： G03F7/70641 ,  G03F1/44 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/705

摘要： A method of identifying and defining forbidden pitches or forbidden pitch ranges for a lithographic exposure tool under a given set of exposure conditions is provided. In the method, a computer simulation is performed, and its results are compared to frequently used pitches to see if such frequently used pitches may yield depth-of-focus (DOF) values greater than the focus budget for the exposure tool. If so, a verification test is performed by using a test mask and actually exposing a surface with the same pattern pitches simulated. From this, actual DOF values are obtained and compared to the focus budget of the exposure tool. Any pitches having a DOF value greater than the focus budget are designated as forbidden pitches. This forbidden pitch information may be integrated into a design rule to restrict the use of such forbidden pitches under the given exposure conditions where they are likely to arise.

摘要翻译： 提供了一种在给定的曝光条件下识别和限定光刻曝光工具的禁止间距或禁止间距范围的方法。 在该方法中，执行计算机模拟，并将其结果与经常使用的间距进行比较，以查看这种经常使用的间距是否可以产生比曝光工具的焦点预算大的焦点深度（DOF）值。 如果是这样，则通过使用测试掩模执行验证测试，并且实际上暴露出模拟相同模式间距的表面。 从此，获得实际的DOF值，并与曝光工具的焦点预算进行比较。 DOF值大于焦点预算的任何间距都被指定为禁止间距。 该禁止音调信息可以被集成到设计规则中，以限制在可能出现的给定曝光条件下使用这种禁止间距。

公开(公告)号：US07496862B2

公开(公告)日：2009-02-24

申请号：US11512823

申请日：2006-08-29

申请人： Mi-Chang Chang ,  Su-Ya Lin ,  Jen-Hang Yang ,  Li-Chun Tien

发明人： Mi-Chang Chang ,  Su-Ya Lin ,  Jen-Hang Yang ,  Li-Chun Tien

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L27/0207 ,  H01L27/11807

摘要： This invention discloses a method for automatically adjusting cell layout height and transistor width of one type of MOS IC cells, the method comprising following steps of Boolean logic operations on at least one such cell: identifying one or more MOS transistor active areas (ODs) and one or more power ODs in an OD layer, expanding the MOS transistor ODs in a predetermined direction by a first predetermined amount, shifting the power ODs in the predetermined direction by a second predetermined amount, expanding one or more MOS transistor gate areas in the predetermined direction by a third predetermined amount, shifting one or more power OD contacts in the predetermined direction by approximately the second predetermined amount, and stretching one or more metal areas (M1s) in a metal layer that is directly coupled to the OD layer through contacts electronically, in the predetermined direction by a predetermined way.

摘要翻译： 本发明公开了一种用于自动调整一个类型的MOS IC单元的单元布局高度和晶体管宽度的方法，所述方法包括以下步骤：对至少一个这样的单元进行布尔逻辑运算：识别一个或多个MOS晶体管有源区（OD）和 在OD层中的一个或多个功率OD，将预定方向上的MOS晶体管OD扩展第一预定量，将预定方向上的功率OD移动第二预定量，将预定的一个或多个MOS晶体管栅极区域扩展 方向移动第三预定量，将一个或多个功率OD触点沿预定方向移动大约第二预定量，以及通过电子接触在一个金属层中直接连接到OD层的金属层中拉伸一个或多个金属区域（M1） ，以预定的方式在预定方向上。

公开(公告)号：US20080059916A1

公开(公告)日：2008-03-06

申请号：US11512823

申请日：2006-08-29

申请人： Mi-Chang Chang ,  Su-Ya Lin ,  Jen-Hang Yang ,  Li-Chun Tien

发明人： Mi-Chang Chang ,  Su-Ya Lin ,  Jen-Hang Yang ,  Li-Chun Tien

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L27/0207 ,  H01L27/11807

摘要： This invention discloses a method for automatically adjusting cell layout height and transistor width of one type of MOS IC cells, the method comprising following steps of Boolean logic operations on at least one such cell: identifying one or more MOS transistor active areas (ODs) and one or more power ODs in an OD layer, expanding the MOS transistor ODs in a predetermined direction by a first predetermined amount, shifting the power ODs in the predetermined direction by a second predetermined amount, expanding one or more MOS transistor gate areas in the predetermined direction by a third predetermined amount, shifting one or more power OD contacts in the predetermined direction by approximately the second predetermined amount, and stretching one or more metal areas (M1s) in a metal layer that is directly coupled to the OD layer through contacts electronically, in the predetermined direction by a predetermined way.

摘要翻译： 本发明公开了一种用于自动调整一个类型的MOS IC单元的单元布局高度和晶体管宽度的方法，所述方法包括以下步骤：对至少一个这样的单元进行布尔逻辑运算：识别一个或多个MOS晶体管有源区（OD）和 在OD层中的一个或多个功率OD，将预定方向上的MOS晶体管OD扩展第一预定量，将预定方向上的功率OD移动第二预定量，将预定的一个或多个MOS晶体管栅极区域扩展 方向移动第三预定量，将一个或多个功率OD触点沿预定方向移动大约第二预定量，以及通过电子接触在一个金属层中直接连接到OD层的金属层中拉伸一个或多个金属区域（M1） ，以预定的方式在预定方向上。

公开(公告)号：US20060273391A1

公开(公告)日：2006-12-07

申请号：US11142214

申请日：2005-06-01

申请人： Carlos Diaz ,  Mi-Chang Chang

发明人： Carlos Diaz ,  Mi-Chang Chang

IPC分类号： H01L29/76

CPC分类号： H01L29/42368 ,  H01L21/26586 ,  H01L21/28247 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/66659

摘要： A preferred embodiment of the invention provides a semiconductor fabrication method. An embodiment comprises forming a MOS device and thermally oxidizing the MOS device to form a gate dielectric substantially thicker at a gate dielectric edge than that at a gate dielectric center. Embodiments further comprise performing a source/drain ion implant to form an asymmetric source/drain, wherein the source region includes a high leakage source junction, and wherein the drain region includes a low leakage drain junction. Other embodiments of the invention comprise a MOS device formed in a semiconductor substrate, wherein the device has improved resistance to floating body effects. Still other embodiments include a CMOS device for low power integrated circuits.

摘要翻译： 本发明的优选实施例提供半导体制造方法。 一个实施例包括形成MOS器件和热氧化MOS器件，以形成栅极电介质在门电介质边缘处比在栅介质中心处基本上更厚的栅极电介质。 实施例还包括执行源极/漏极离子注入以形成非对称源极/漏极，其中源极区域包括高泄漏源极结，并且其中漏极区域包括低泄漏漏极结。 本发明的其它实施例包括形成在半导体衬底中的MOS器件，其中该器件具有改善的对浮体效应的抵抗力。 其他实施例包括用于低功率集成电路的CMOS器件。

公开(公告)号：US5744865A

公开(公告)日：1998-04-28

申请号：US735356

申请日：1996-10-22

申请人： Shin-Puu Jeng ,  Mi-Chang Chang

发明人： Shin-Puu Jeng ,  Mi-Chang Chang

IPC分类号： H01L21/768 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/3672 ,  H01L21/76801 ,  H01L21/76834 ,  H01L23/3732 ,  H01L21/76837 ,  H01L2924/0002

摘要： A method and structure for improving the thermal conductivity and therefore the heat dissipation of densely interconnected semiconductor circuits, particularly those utilizing low dielectric constant materials by placing a layer of highly thermally conductive material such as diamond film 26 between layers of interconnect metal 22. An embodiment of the present invention allows increased thermal conductivity from the upper levels of metalization to the substrate 10 where structure of the present invention is repeated to form multiple levels of interconnects stacked one upon the other. Further, the diamond layer of the present invention may be used as an effective etch stop or planarization stop. The present invention can be used with known low dielectric constant materials, interlevel dielectrics 30 and planarization techniques with the added benefit of highly thermally conductive diamond film.

摘要翻译： 一种用于改善密集互连的半导体电路的导热性和因此散热的方法和结构，特别是那些利用低介电常数材料的那些，通过在互连金属22的层之间放置诸如金刚石膜26之类的高导热性材料层。 本发明允许从上层金属化到衬底10的热导率增加，其中重复本发明的结构以形成彼此层叠的多层互连。 此外，本发明的金刚石层可以用作有效的蚀刻停止或平坦化停止。 本发明可以与已知的低介电常数材料，层间电介质30和具有高导热性金刚石膜的附加益处的平面化技术一起使用。

公开(公告)号：US06813757B2

公开(公告)日：2004-11-02

申请号：US10113403

申请日：2002-04-01

申请人： Thomas J. Aton ,  Mi-Chang Chang

发明人： Thomas J. Aton ,  Mi-Chang Chang

IPC分类号： G06F1750

CPC分类号： G03F7/705 ,  G03F1/68 ,  G03F7/70608 ,  G06F17/5081

摘要： A method for evaluating a mask pattern for a product that is manufactured by a process that is described at least in part by a mathematical process model includes the steps of: (a) selecting a reference locus; (b) determining a sampling direction from the reference locus; (c) selecting a sampling locus in the sampling direction; (d) evaluating a model factor at the sampling locus; and (e) applying at least one predetermined criterion to the model factor to determine a conclusion. If the conclusion is a first inference, (f) repeating steps (c) through (e). If the conclusion is a second inference, (g) determining whether the evaluation is complete and repeating steps (a) through (g) until the evaluating is complete.

摘要翻译： 用于评估通过至少部分地由数学过程模型描述的处理制造的产品的掩模图案的方法包括以下步骤：（a）选择参考轨迹; （b）从参考轨迹确定采样方向; （c）选择取样方向的取样轨迹; （d）评估抽样点的模型因子; 和（e）对模型因子应用至少一个预定标准以确定结论。 如果结论是第一个推论，（f）重复步骤（c）至（e）。 如果结论是第二个推论，（g）确定评估是否完成，并重复步骤（a）至（g），直到评估结束。