Abstract:
An apparatus determines a code block size (CBS) of information bits contained in a codeword of low-density parity check (LDPC) coding. The apparatus compares the CBS with at least one threshold, determines, based on a result of the comparison, a Kb number and determines a Kp number based on a code rate and the Kb number. The apparatus generates a parity check matrix. An information portion of the parity check matrix is a first matrix formed by M number of second square matrices. M is equal to Kp multiplied by Kb. A total number of columns in the Kb number of second square matrices is equal to a total number of bits of the CBS. One or more matrices of the M number of second square matrices are circular permutation matrices. The apparatus operates an LDPC encoder or an LDPC decoder based on the parity check matrix.
Abstract:
Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.
Abstract:
Concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code are described. A processor of an apparatus may generate a quasi-cyclic-low-density parity-check (QC-LDPC) code and encode data using the selected codebook. In generating the QC-LDPC code, the processor may define a plurality of sets of lifting factors, generate a respective table of shift values for each lifting factor of the plurality of sets of lifting factors, and generate the QC-LDPC code using a base matrix and the shift coefficient table.
Abstract:
Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.
Abstract:
Concepts and schemes pertaining to information coding for mobile communications are described. A processor of an apparatus encodes data to provide encoded data. The processor also transmits the encoded data to a network node of a wireless network. In encoding the data, the processor encodes the data with a low-density parity-check (LDPC) code to provide LDPC-coded data. Moreover, the processor processes the LDPC-coded data with a forward error correction (FEC) robustness enhancement function to provide the encoded data. The FEC robustness enhancement function includes an interleaving function that interleaves the LDPC-coded data to provide the encoded data, an interlacing function that interlaces the LDPC-coded data to provide the encoded data, or a bit-reordering function that reorders bits of the LDPC-coded data to provide the encoded data.
Abstract:
A beamforming system synchronization architecture is proposed to allow a receiving device to synchronize to a transmitting device in time, frequency, and spatial domain in the most challenging situation with very high pathloss. A periodically configured time-frequency resource blocks in which the transmitting device uses the same beamforming weights for its control beam transmission to the receiving device. A pilot signal for each of the control beams is transmitted in each of the periodically configured time-frequency resource blocks. The same synchronization signal can be used for all stages of synchronization including initial coarse synchronization, device and beam identification, and channel estimation for data demodulation.
Abstract:
A beamforming system synchronization architecture is proposed to allow a receiving device to synchronize to a transmitting device in time, frequency, and spatial domain in the most challenging situation with very high pathloss. A periodically configured time-frequency resource blocks in which the transmitting device uses the same beamforming weights for its control beam transmission to the receiving device. A pilot signal for each of the control beams is transmitted in each of the periodically configured time-frequency resource blocks. Pilot symbols are inserted into pilot structures and repeated for L times in each pilot structure. The L repetitions can be implemented by one or more Inverse Fast Fourier Transfers (IFFTs) with corresponding one or more cyclic prefix (CP) lengths.
Abstract:
A communications apparatus. A first radio module communicates with a first wireless network and provides wireless communications services. A second radio module communicates with a second wireless network and provides wireless communications services. At least two antennas shared by the first radio module and the second radio module. When the first radio module operates in a connected mode and when the timing of the first radio module performing the first receiving activity coincides with the timing of the second radio module performing a second receiving activity, the first radio module reports a value of 1 for a Rank Indicator to the first wireless network at least once before the second radio module is to perform the second receiving activity, and then the second radio module uses one of the antennas to perform the second receiving activity.
Abstract:
A transceiver architecture with combined digital beamforming and analog/hybrid beamforming is proposed. Digital beamforming is used for beam training with reduced overhead (switching time). It is beneficial to estimate all UE's angle of arrival (AoA) at the same time. In addition, the pilot/training signals are transmitted in a narrow band to reduce complexity. Analog/hybrid beamforming is used for data transmission with high directive gain and low complexity. The value of beamforming weights (phase shifter values) in analog domain can be based on the estimation of AoA from beam training. By using digital beamforming for beam training, combined with analog/hybrid beamforming for data transmission, effective beamforming is achieved with reduced overhead, complexity, and cost.
Abstract:
A transceiver architecture with combined digital beamforming and analog/hybrid beamforming is proposed. Digital beamforming is used for beam training with reduced overhead (switching time). It is beneficial to estimate all UE's angle of arrival (AoA) at the same time. In addition, the pilot/training signals are transmitted in a narrow band to reduce complexity. Analog/hybrid beamforming is used for data transmission with high directive gain and low complexity. The value of beamforming weights (phase shifter values) in analog domain can be based on the estimation of AoA from beam training. By using digital beamforming for beam training, combined with analog/hybrid beamforming for data transmission, effective beamforming is achieved with reduced overhead, complexity, and cost.