公开(公告)号：US20200014945A1

公开(公告)日：2020-01-09

申请号：US16442581

申请日：2019-06-17

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Assaf Weissman ,  Kobi Pines ,  Noam Bloch ,  Erez Yaacov ,  Ariel Naftali Cohen

IPC: H04N19/42 ,  H04N19/105 ,  H04N19/132 ,  H04N19/119 ,  H04N19/176

Abstract: A system including an acceleration device including input circuitry configured, for each of a first plurality of video frames to be encoded, to receive an input including at least one raw video frame and at least one reference frame, and to divide each of the first plurality of video frames to be encoded into a second plurality of blocks, and similarity computation circuitry configured, for each one of the first plurality of video frame to be encoded: for each block of the second plurality of blocks, to produce a score of result blocks based on similarity of each block in each frame to be encoded to every block of the reference frame, an AC energy coefficient, and a displacement vector. Related apparatus and methods are also provided.

公开(公告)号：US10462060B2

公开(公告)日：2019-10-29

申请号：US15896128

申请日：2018-02-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Jacob Ruthstein ,  David Mozes ,  Dror Bohrer ,  Ariel Shahar ,  Lior Narkis ,  Noam Bloch

IPC: H04L12/851 ,  H04L12/26 ,  H04L12/801

Abstract: Packet flows received in a data network are assigned to respective entries of a database. During an accumulation interval byte counts of the assigned packet flows are accumulated in the respective database entries. The packet flows are classified as elephant flows when differences between the byte counts and a reference byte count exceed a threshold and are reported after expiration of the accumulation interval.

公开(公告)号：US10430374B2

公开(公告)日：2019-10-01

申请号：US15196088

申请日：2016-06-29

Applicant: Mellanox Technologies Ltd.

Inventor： Adi Menachem ,  Ariel Shahar ,  Noam Bloch ,  Diego Crupnicoff ,  Michael Kagan

IPC: G06F15/173 ,  H04L29/06 ,  G06F13/28 ,  H04L1/16 ,  H04L1/18

Abstract: A method for data transfer includes transmitting a sequence of data packets, including at least a first packet and a second packet transmitted subsequently to the first packet, from a first computer over a network to a second computer in a single remote direct memory access (RDMA) data transfer transaction. Upon receipt of the second packet at the second computer without previously having received the first packet, a negative acknowledgment (NAK) packet is sent from the second computer over the network to the first computer, indicating that the first packet was not received. In response to the NAK packet, the first packet is retransmitted from the first computer to the second computer without retransmitting the second packet.

公开(公告)号：US20190140979A1

公开(公告)日：2019-05-09

申请号：US16012826

申请日：2018-06-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan Levi ,  Liran Liss ,  Haggai Eran ,  Noam Bloch ,  Idan Burstein ,  Lior Narkis ,  Avraham Ganor

IPC: H04L12/933 ,  G06F9/455 ,  G06F13/40

Abstract: A network interface controller that is connected to a host and a packet communications network. The network interface controller includes electrical circuitry configured as a packet processing pipeline with a plurality of stages. It is determined in the network interface controller that at least a portion of the stages of the pipeline are acceleration-defined stages. Packets are processed in the pipeline by transmitting data to an accelerator from the acceleration-defined stages, performing respective acceleration tasks on the transmitted data in the accelerator, and returning processed data from the accelerator to receiving stages of the pipeline.

公开(公告)号：US20190081904A1

公开(公告)日：2019-03-14

申请号：US15701459

申请日：2017-09-12

Applicant: Mellanox Technologies, Ltd.

Inventor： Dror Bohrer ,  Noam Bloch ,  Lior Narkis ,  Hillel Chapman ,  Gilad Hammer

IPC: H04L12/863 ,  H04L12/813 ,  G06F9/455

CPC classification number: H04L47/6235 ,  G06F9/45558 ,  G06F2009/45595 ,  H04L45/74 ,  H04L47/20 ,  H04L49/70

Abstract: Network interface apparatus includes a host interface and a network interface, which receives packets in multiple packet flows destined for one or more virtual machines running on a host processor. Packet processing circuitry receives a first instruction from the host processor to offload preprocessing of the data packets in a specified flow in accordance with a specified rule, and initiates preprocessing of the data packets while writing one or more initial data packets from the specified flow to a temporary buffer. Upon subsequently receiving a second instruction to enable the specified rule, the initial data packets are delivered from the temporary buffer, after preprocessing by the packet processing circuitry, directly to a virtual machine to which the specified flow is destined, followed by preprocessing and delivery of subsequent data packets in the specified flow to the virtual machine.

公开(公告)号：US10164905B2

公开(公告)日：2018-12-25

申请号：US14608265

申请日：2015-01-29

Applicant: Mellanox Technologies Ltd.

Inventor： Ofer Hayut ,  Noam Bloch ,  Shlomo Raikin ,  Liran Liss

IPC: H04L12/803 ,  H04L12/721 ,  H04L12/931

Abstract: A Network Interface Controller (NIC) includes a network interface, a peer interface and steering logic. The network interface is configured to receive incoming packets from a communication network. The peer interface is configured to communicate with a peer NIC not via the communication network. The steering logic is configured to classify the packets received over the network interface into first incoming packets that are destined to a local Central Processing Unit (CPU) served by the NIC, and second incoming packets that are destined to a remote CPU served by the peer NIC, to forward the first incoming packets to the local CPU, and to forward the second incoming packets to the peer NIC over the peer interface not via the communication network.

公开(公告)号：US10082858B2

公开(公告)日：2018-09-25

申请号：US14745549

申请日：2015-06-22

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Idan Burstein ,  Shlomo Raikin ,  Noam Bloch

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3209

Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having multiple host resources, information regarding respective power states of the host resources. The data are selectively directed from the peripheral device to the host resources responsively to the respective power states.

公开(公告)号：US20180102976A1

公开(公告)日：2018-04-12

申请号：US15836869

申请日：2017-12-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Michael Kagan ,  Noam Bloch

IPC: H04L12/851 ,  H04L29/00 ,  G06F13/30

Abstract: A network interface controller includes a host interface, which is configured to be coupled to a host processor having a host memory. A network interface is configured to receive data packets from a network, each data packet including a header, which includes header fields, and a payload including data. Packet processing circuitry is configured to process one or more of the header fields and at least a part of the data and to select, responsively at least to the one or more of the header fields, a location in the host memory. The circuitry writes the data to the selected location and upon determining that the processed data satisfies a predefined criterion, asserts an interrupt on the host processor so as to cause the host processor to read the data from the selected location in the host memory.

公开(公告)号：US09639464B2

公开(公告)日：2017-05-02

申请号：US13628155

申请日：2012-09-27

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Haggai Eran ,  Shachar Raindel ,  Liran Liss ,  Noam Bloch

IPC: G06F12/08 ,  G06F12/1081

CPC classification number: G06F12/08 ,  G06F12/1081

Abstract: A method for data transfer includes receiving in an operating system of a host computer an instruction initiated by a user application running on the host processor identifying a page of virtual memory of the host computer that is to be used in receiving data in a message that is to be transmitted over a network to the host computer but has not yet been received by the host computer. In response to the instruction, the page is loaded into the memory, and upon receiving the message, the data are written to the loaded page.

公开(公告)号：US09344490B2

公开(公告)日：2016-05-17

申请号：US14324246

申请日：2014-07-07

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Noam Bloch ,  Gil Bloch ,  Ariel Shachar ,  Hillel Chapman ,  Ishai Rabinobitz ,  Pavel Shamis ,  Gilad Shainer

IPC: G06F9/54 ,  H04L29/08

CPC classification number: H04L67/10 ,  G06F9/546 ,  G06F2209/509

Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

Abstract translation: 网络接口（NI）包括主机接口，其被配置为从节点的主机处理器接收从要由节点执行的操作导出的一个或多个跨通道工作请求。 NI包括用于通过网络向一个或多个对等节点执行传输信道的多个工作队列。 NI还包括控制电路，其被配置为经由主机接口接受跨通道工作请求，并且通过根据一个或多个控制电路控制至少一个给定的工作队列的前进来执行使用工作队列的跨通道工作请求 这取决于一个或多个其他工作队列的完成状态，以便执行操作。