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    Logical-to-physical mapping using a flag to indicate whether a mapping entry points to [[for]] sequentially stored data
    62.
    发明授权
    Logical-to-physical mapping using a flag to indicate whether a mapping entry points to [[for]] sequentially stored data 有权

    公开(公告)号：US11507518B2

    公开(公告)日：2022-11-22

    申请号：US16870674

    申请日：2020-05-08

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe Cariello ,  Jonathan S. Parry

    IPC: G06F12/1009

    Abstract: Methods, systems, and devices for compressed logical-to-physical mapping for sequentially stored data are described. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block address generated by a host device to physical addresses of the memory device. The memory device may determine whether all of the entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all of the entries contain consecutive physical addresses, the memory device may store a starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than pointing to a terminal logical-to-physical mapping table. The memory device may, for subsequent reads of data stored in one or more of the consecutive physical addresses, bypass the terminal table to read the data.

    POWER ARCHITECTURE FOR NON-VOLATILE MEMORY
    64.
    发明申请
    POWER ARCHITECTURE FOR NON-VOLATILE MEMORY 有权

    公开(公告)号：US20220254418A1

    公开(公告)日：2022-08-11

    申请号：US17168970

    申请日：2021-02-05

    Applicant: Micron Technology, Inc.

    Inventor： Qisong Lin ,  Shuai Xu ,  Jonathan S. Parry ,  Jeremy Binfet ,  Michele Piccardi ,  Qing Liang

    IPC: G11C16/30 ,  G06F3/06 ,  G06F12/0875 ,  G11C16/10

    Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.

    PURGING DATA AT A MEMORY DEVICE
    65.
    发明申请
    PURGING DATA AT A MEMORY DEVICE 有权

    公开(公告)号：US20220164487A1

    公开(公告)日：2022-05-26

    申请号：US17524471

    申请日：2021-11-11

    Applicant: Micron Technology, Inc.

    Inventor： Christian M. Gyllenskog ,  Jonathan S. Parry

    IPC: G06F21/79 ,  G06F21/60 ,  G06F21/54 ,  G06F12/02

    Abstract: Methods, systems, and devices for purging data from a memory device are described. A memory system may receive, from a host system, a command to write data to an address storing an encryption key in a first portion of the memory system that is configured to store secure information (e.g., a Replay Protected Memory Block). The encryption key may be configured to encrypt data associated with the host system that is stored in a second portion of the memory system. The memory system may then receive an indication of a purge command from the host system. The memory system may execute the purge command by transferring data from the first portion of the memory system to a third portion of the memory system configured to store secure information and erasing the data from the first portion of the memory system.

    ACCESS OPERATION STATUS SIGNALING FOR MEMORY SYSTEMS
    66.
    发明申请
    ACCESS OPERATION STATUS SIGNALING FOR MEMORY SYSTEMS 有权

    公开(公告)号：US20210382769A1

    公开(公告)日：2021-12-09

    申请号：US16891615

    申请日：2020-06-03

    Applicant: Micron Technology, Inc.

    Inventor： Qing Liang ,  Jonathan S. Parry ,  Giuseppe Cariello ,  Deping He

    IPC: G06F11/07 ,  G06F11/30

    Abstract: Techniques for access operation status signaling for memory systems are described. In some examples, a memory system may respond to access commands from a host system by performing access operations such as read or write operations. In accordance with examples as disclosed herein, a system may be configured to support access operation status signaling between a host system and a memory system, which may improve the ability of the system to adapt to various access scenarios, including when access operation completion is delayed. For example, when a memory system is performing an error recovery or media management operation, the memory system may indicate that the error recovery or media management operation is being performed or is otherwise ongoing. Such status signaling may indicate that the memory system is actively performing operations, which may be used to inhibit a reset or reinitialization by a host system.

    DATA TECHNIQUES FOR SYSTEM BOOT PROCEDURES
    67.
    发明申请
    DATA TECHNIQUES FOR SYSTEM BOOT PROCEDURES 有权

    公开(公告)号：US20210373908A1

    公开(公告)日：2021-12-02

    申请号：US16888212

    申请日：2020-05-29

    Applicant: Micron Technology, Inc.

    Inventor： Qing Liang ,  Jonathan S. Parry ,  Nadav Grosz

    IPC: G06F9/4401 ,  G06F12/10

    Abstract: Methods, systems, and devices for data techniques for system boot procedures are described. A memory system may receive, from a host system, a set of commands as part of a boot procedure of the host system. The set of commands may request data stored in a first set of locations of a memory array of the memory system. The memory system may retrieve, as part of the boot procedure, the data from the first set of locations based on receiving the commands. The memory system may determine an order that the data is retrieved from each location of the first set of locations. The memory system may transfer the data from the first set of locations to a second set of locations based on the order that the data is retrieved from each location of the first set of locations.

    READ PREDICTION DURING A SYSTEM BOOT PROCEDURE
    68.
    发明申请
    READ PREDICTION DURING A SYSTEM BOOT PROCEDURE 有权

    公开(公告)号：US20210373907A1

    公开(公告)日：2021-12-02

    申请号：US16888198

    申请日：2020-05-29

    Applicant: Micron Technology, Inc.

    Inventor： Qing Liang ,  Nadav Grosz ,  Jonathan S. Parry

    IPC: G06F9/4401 ,  G06F12/0877

    Abstract: Methods, systems, and devices for read prediction during a system boot procedure are described. A memory device may identify a command for a boot procedure and transfer data stored in a memory array to a cache of the memory device. In some cases, the memory device may prefetch data used during the boot procedure and thereby improve the latency of the boot procedure. When the memory device receives a command that requests data stored in the memory array as part of the boot procedure, the memory device may identify a cache hit based on prefetching the requested data before the command is received. In such cases, the memory device may retrieve the prefetched data from the cache.

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