公开(公告)号：US11443780B2

公开(公告)日：2022-09-13

申请号：US17172257

申请日：2021-02-10

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Beau D. Barry ,  Tae H. Kim ,  Christopher J. Kawamura

IPC: G11C7/10 ,  G11C7/06 ,  G11C16/32 ,  G11C16/30

Abstract: An access line multiplexor can be formed under vertically stacked tiers of memory cells. The multiplexor can include a first transistor coupled to a vertical access line, to a horizontal access line, and to a second transistor. The second transistor can be coupled to a power supply. The transistors can be n-type metal oxide semiconductor transistors.

公开(公告)号：US20220277784A1

公开(公告)日：2022-09-01

申请号：US17746542

申请日：2022-05-17

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Tae H. Kim

IPC: G11C11/4091 ,  G11C5/06 ,  G11C11/4096 ,  G11C11/404 ,  H03K19/173

Abstract: A sense amplifier can be formed outside of/horizontally adjacent to an array of vertically stacked tiers of memory cells. Memory cells can be sensed via multiplexors formed under the array that can operate to couple vertical sense lines (to which the memory cells are coupled) to horizontal sense lines (to which the sense amplifier is coupled).

公开(公告)号：US20220068358A1

公开(公告)日：2022-03-03

申请号：US17006097

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim

IPC: G11C11/4093 ,  H03K3/356 ,  H03K19/0185

Abstract: A memory device includes a level down shifting driver circuit. The level down shifting driver circuit include input circuitry having at least one input port, and a cross-junction circuitry electrically coupled to the input circuitry and configured to receive a first signal from the input circuitry to drive one or more devices included in the cross-junction circuitry. The level down shifting driver circuit further includes an output drive circuitry electrically coupled to the cross-junction circuitry and configured to receive a second signal from the cross-junction circuitry, wherein the output drive circuitry comprises an output line configured to deliver a first voltage output based on a first input voltage received by the input circuitry, and a second voltage output based on a second input voltage received by the input circuitry.

公开(公告)号：US10978138B2

公开(公告)日：2021-04-13

申请号：US17015889

申请日：2020-09-09

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Christopher J. Kawamura

IPC: G11C7/22 ,  G11C11/408 ,  G11C11/4076

Abstract: A main word line circuit provides a first and second row factor signals. The main word line circuit includes a pull-up circuit to drive a global word line to follow a first decoded address signal when the first row factor signal is at a first value. The main word line circuit includes an intermediate voltage circuit to drive the global word line to follow a value of the second row factor signal. A processing device drives the global word line to an active state by setting the first row factor signal to the first value when the first decoded address signal is at a high state, and drives the global word line to follow a value of the second row factor signal by setting the first row factor signal to the second value while the first decoded address signal is at the high state.

公开(公告)号：US10896706B2

公开(公告)日：2021-01-19

申请号：US16399159

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Tae H. Kim

IPC: G11C8/08 ,  G11C11/408

Abstract: A FX phase driver for a memory device having a first driver circuit including a first pull-up circuit configured to drive a first phase signal to a first high state value and a first pull-down circuit configured to drive the first phase signal to a first low state value. The phase driver also including a second driver circuit including a second pull-up circuit configured to drive a second phase signal to a second high state value that is higher than an active state voltage level of a word line in the memory device and a second pull-down circuit configured to drive the second phase signal to a second low state value. The second pull-down circuit includes a stabilization circuit configured to provide a resistive path for a leakage current in the second pull-down circuit when the second pull-up circuit drives the second phase signal to the second high state value.

公开(公告)号：US20200350011A1

公开(公告)日：2020-11-05

申请号：US16399197

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Tae H. Kim

IPC: G11C13/00 ,  G11C8/08

Abstract: A sub-word line circuit having a phase driver circuit to provide a first phase signal and a second phase signal. The sub-word line circuit includes a sub-word line driver circuit having a pull-up circuit configured to receive the first phase signal and a global word line signal. The pull-circuit is further configured to drive a local word line to follow the global word line signal when the first phase signal is at a first value and isolate the local word line from the global word line signal when the first phase signal is at a second value. The sub-word line circuit also includes a processing device that sets the first phase signal to the first value prior to the global word line signal entering an active state and sets the first phase signal to the second value only after the global word line signal has entered a pre-charge state.

公开(公告)号：US20200349999A1

公开(公告)日：2020-11-05

申请号：US16399283

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Kawamura ,  Charles L. Ingalls ,  Tae H. Kim

IPC: G11C11/408 ,  G11C11/4076

Abstract: An apparatus includes a plurality of main word line circuits. Each main word line circuit drives a respective global word line to one of an active state value, an intermediate voltage state, or a pre-charge state. The intermediate voltage state voltage is below the active state voltage and above the pre-charge state voltage. The memory device also includes a plurality of sub-word line drivers. Each sub-word line driver is connected to a corresponding global word line and configured to drive a respective local word line between the corresponding global word line voltage and a low voltage value. The apparatus further includes a plurality of phase drivers. Each phase driver is connected to a predetermined number of sub-word line drivers, where each of the predetermined number of sub-word line drivers connects to a different global word line.

公开(公告)号：US20200349998A1

公开(公告)日：2020-11-05

申请号：US16399235

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Christopher J. Kawamura

IPC: G11C11/408 ,  G11C11/4076

Abstract: A main word line circuit provides a first and second row factor signals. The main word line circuit includes a pull-up circuit to drive a global word line to follow a first decoded address signal when the first row factor signal is at a first value. The main word line circuit includes an intermediate voltage circuit to drive the global word line to follow a value of the second row factor signal. A processing device drives the global word line to an active state by setting the first row factor signal to the first value when the first decoded address signal is at a high state, and drives the global word line to follow a value of the second row factor signal by setting the first row factor signal to the second value while the first decoded address signal is at the high state.

公开(公告)号：US20200160893A1

公开(公告)日：2020-05-21

申请号：US16747824

申请日：2020-01-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Kawamura ,  Tae H. Kim

IPC: G11C7/06 ,  G11C11/4074 ,  G11C7/12 ,  G11C8/10 ,  G11C11/4091

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state, and a sense amplifier configured to, during a sense operation, couple a first gut node to the first digit line and couple a second gut node to a second digit line in response to an isolation signal. The sense amplifier is further configured to, after the first gut node is coupled to the first digit line and the second gut node is coupled to the second digit line, drive the first digit line to a first sense voltage of a first control signal and drive the second digit line to a second sense voltage of a second control signal based on a data state of the memory cell.

公开(公告)号：US20200051608A1

公开(公告)日：2020-02-13

申请号：US16523653

申请日：2019-07-26

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Tae H. Kim ,  Charles L. Ingalls

IPC: G11C11/4074 ,  G11C11/408 ,  G11C11/4091

Abstract: A memory device is provided. The memory device includes a memory array having at least one memory cell. The memory device further includes a sense amplifier circuit configured to read data from the at least one memory cell, write data to the at least one memory cell, or a combination thereof. The memory device additionally includes a first bus configured to provide a first electric power to the sense amplifier circuit, and a second bus configured to provide a second electric power to a second circuit, wherein the first bus and the second bus are configured to be electrically coupled to each other to provide for the first electric power and the second electric power to the at least one memory cell.