-
公开(公告)号：US10950316B2
公开(公告)日：2021-03-16
申请号：US16990137
申请日：2020-08-11
发明人： Violante Moschiano , Tecla Ghilardi , Tommaso Vali , Emilio Camerlenghi , William C. Filipiak , Andrea D'Alessandro
IPC分类号： G11C16/26 , G11C16/34 , G11C5/06 , G11C11/413 , G11C8/08
摘要： Apparatus having plurality of data lines each selectively connected to a respective string of series-connected memory cells, a plurality of registers each configured to indicate a state of a respective data line, and logic configured to indicate when each data line of the plurality of data lines has a particular state might facilitate determination of a pass voltage of a read operation.
-
公开(公告)号：US10950312B2
公开(公告)日：2021-03-16
申请号：US16458384
申请日：2019-07-01
摘要： Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.
-
公开(公告)号：US10891187B2
公开(公告)日：2021-01-12
申请号：US16516510
申请日：2019-07-19
IPC分类号： G11C29/00 , G06F11/10 , G11C11/56 , G11C16/04 , G11C16/10 , G06F3/06 , G06F12/02 , G06F12/06 , G11C29/52
摘要： A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure different blocks of the plurality of blocks of memory cells in different configurations, which can include blocks configured to include only groups of user data memory cells for storing user data, blocks configured to include only groups of overhead data memory cells for storing error correction code (ECC) data, and blocks configured to include groups of user data memory cells and groups of overhead data memory cells.
-
公开(公告)号：US20200372961A1
公开(公告)日：2020-11-26
申请号：US16990137
申请日：2020-08-11
发明人： Violante Moschiano , Tecla Ghilardi , Tommaso Vali , Emilio Camerlenghi , William C. Filipiak , Andrea D'Alessandro
IPC分类号： G11C16/34 , G11C16/26 , G11C8/08 , G11C11/413 , G11C5/06
摘要： Apparatus having plurality of data lines each selectively connected to a respective string of series-connected memory cells, a plurality of registers each configured to indicate a state of a respective data line, and logic configured to indicate when each data line of the plurality of data lines has a particular state might facilitate determination of a pass voltage of a read operation.
-
公开(公告)号：US20200372960A1
公开(公告)日：2020-11-26
申请号：US16989191
申请日：2020-08-10
摘要： Memory having an array of memory cells and configured to store a first value representative of a characteristic sensed from a first data line, store a second value representative of the characteristic sensed from a second data line, perform an operation on the first value and the data value at a first logic circuitry, and perform an operation on an output of the first logic circuitry and a threshold data value at a second logic circuitry.
-
公开(公告)号：US20200321065A1
公开(公告)日：2020-10-08
申请号：US16908832
申请日：2020-06-23
发明人： Tommaso Vali , Ramin Ghodsi
摘要： Methods of operating a memory, as well as memory configured to perform such methods, might include determining a plurality of read voltages for a read operation during a precharge phase of the read operation, determining a pass voltage for the read operation during the precharge phase of the read operation, applying the pass voltage to each unselected access line of a plurality of access lines, and, for each read voltage of the plurality of read voltages, applying that read voltage to a selected access line of the plurality of access lines and sensing a data state of a memory cell connected to the selected access line.
-
公开(公告)号：US10777286B2
公开(公告)日：2020-09-15
申请号：US16267488
申请日：2019-02-05
发明人： Violante Moschiano , Tecla Ghilardi , Tommaso Vali , Emilio Camerlenghi , William C. Filipiak , Andrea D'Alessandro
IPC分类号： G11C16/26 , G11C16/34 , G11C8/08 , G11C11/413 , G11C5/06
摘要： Methods of operating a memory, and memory configured to perform similar methods, might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, ceasing increasing the voltage level applied to each access line of the plurality of access lines in response to the state of each data line of the plurality of data lines having a particular condition, changing a voltage level applied to a particular access line of the plurality of access lines to a particular voltage level, and sensing a state of each data line of a subset of the plurality of data lines while applying the particular voltage level to the particular access line.
-
公开(公告)号：US10529430B2
公开(公告)日：2020-01-07
申请号：US16180154
申请日：2018-11-05
摘要： Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.
-
公开(公告)号：US10482972B2
公开(公告)日：2019-11-19
申请号：US16413708
申请日：2019-05-16
摘要： Memories include a data line, a plurality of strings of series-connected memory cells selectively connected to the data line, a plurality of first access lines each coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a plurality of second access lines each coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells.
-
公开(公告)号：US20190340065A1
公开(公告)日：2019-11-07
申请号：US16516510
申请日：2019-07-19
IPC分类号： G06F11/10 , G11C29/52 , G06F3/06 , G06F12/06 , G11C16/04 , G06F12/02 , G11C16/10 , G11C11/56
摘要： A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure different blocks of the plurality of blocks of memory cells in different configurations, which can include blocks configured to include only groups of user data memory cells for storing user data, blocks configured to include only groups of overhead data memory cells for storing error correction code (ECC) data, and blocks configured to include groups of user data memory cells and groups of overhead data memory cells.
-
-
-
-
-
-
-
-
-
搜索结果
145 条记录 (耗时 0.023 秒)
