公开(公告)号：US20210141530A1

公开(公告)日：2021-05-13

申请号：US17157410

申请日：2021-01-25

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Mauro Luigi Sali ,  Stefano Falduti ,  Ugo Russo

IPC: G06F3/06

Abstract: Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.

公开(公告)号：US10901622B2

公开(公告)日：2021-01-26

申请号：US16236040

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Mauro Luigi Sali ,  Stefano Falduti ,  Ugo Russo

IPC: G06F3/06

Abstract: Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.

公开(公告)号：US20190198065A1

公开(公告)日：2019-06-27

申请号：US15926427

申请日：2018-03-20

Applicant: Micron Technology, Inc.

Inventor： Ugo Russo

IPC: G11C7/10 ,  G11C19/32 ,  G11C11/56 ,  H01L27/11524

CPC classification number: G11C7/1006 ,  G11C7/1096 ,  G11C11/5621 ,  G11C19/32 ,  H01L27/11524

Abstract: Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another. Some embodiments include methods of forming assemblies.

公开(公告)号：US20170221965A1

公开(公告)日：2017-08-03

申请号：US15487743

申请日：2017-04-14

Applicant: Micron Technology, Inc.

Inventor： Ugo Russo ,  Andrea Redaelli ,  Giorgio Servalli

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608

Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.

公开(公告)号：US20150138880A1

公开(公告)日：2015-05-21

申请号：US14596293

申请日：2015-01-14

Applicant: Micron Technology, Inc.

Inventor： Ugo Russo ,  Andrea Redaelli ,  Fabio Pellizzer

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C11/5678 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/008 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/16

Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.

Abstract translation: 具有多个电阻变化材料的电阻变量存储单元及其操作和形成方法在此描述。 作为示例，电阻可变存储单元可以包括位于插塞材料和电极材料之间的多个电阻变化材料。 电阻可变存储单元还包括接触插塞材料和多个电阻可变材料中的每一个的第一导电材料和接触电极材料和多个电阻可变材料中的每一个的第二导电材料。