公开(公告)号：US10482953B1

公开(公告)日：2019-11-19

申请号：US16103022

申请日：2018-08-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan Lin ,  Yu-Yu Lin ,  Feng-Min Lee ,  Chao-Hung Wang ,  Po-Hao Tseng ,  Kai-Chieh Hsu

IPC: G11C11/56 ,  H01L27/22 ,  H01L27/24

Abstract: A multi-state memory device includes a first memory element, a second memory element, a first controlling element and a second controlling element. The second memory element has a memory cell structure identical to that of the first memory element and connects to the first memory element in series. The first controlling element is connected to the first memory element either in series or in parallel. The second controlling element has a characteristic value identical to that of the first controlling element and is connected to the second memory element by a connection structure identical to that of the first controlling element. When the first memory element receives a first signal and a second signal through the first controlling element, a first state value and a second state value are generated correspondingly, and the characteristic value is greater than the first state value and less than the second state value.

公开(公告)号：US10332840B2

公开(公告)日：2019-06-25

申请号：US15464377

申请日：2017-03-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Kai-Chieh Hsu

IPC: H01L27/112 ,  H01L23/535 ,  H01L23/00 ,  G11C7/10 ,  G11C7/24 ,  G11C17/16

Abstract: A semiconductor device includes a programmable memory array comprising plural memory units disposed above a substrate. One of the memory units comprises a gate electrode disposed above the substrate, a conductive portion spaced apart from the gate electrode, and a dielectric layer contacting the conductive portion and separated from the gate electrode, and the dielectric layer defining a threshold voltage of the related memory unit, wherein at least two of the memory units have different threshold voltages.

公开(公告)号：US20190067574A1

公开(公告)日：2019-02-28

申请号：US15690353

申请日：2017-08-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Po-Hao Tseng ,  Kai-Chieh Hsu

IPC: H01L45/00 ,  H05K3/34

CPC classification number: H01L45/1641 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0083 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H05K3/3494

Abstract: A method for treating a semiconductor structure is provided. A semiconductor structure comprising memory devices is provided. A forming process is conducted to initialize operation of the memory devices. The semiconductor structure is subjected to a forming thermal treatment, and step of saving data to the memory devices is performed after the forming thermal treatment.

公开(公告)号：US09859336B1

公开(公告)日：2018-01-02

申请号：US15401155

申请日：2017-01-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Feng-Min Lee

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/2463 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

Abstract: A semiconductor device including a memory cell structure is provided, and the memory cell structure includes an insulating layer disposed above a substrate, a bottom electrode embedded in the insulating layer, a resistance switching layer disposed on the bottom electrode, and a top electrode disposed on the resistance switching layer and covering the resistance switching layer. Also, the bottom electrode has a concave top surface lower than a flat upper surface of the insulating layer.

公开(公告)号：US09853215B1

公开(公告)日：2017-12-26

申请号：US15365985

申请日：2016-12-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Feng-Min Lee

IPC: H01L45/00

CPC classification number: H01L45/1266 ,  H01L45/08

Abstract: A resistance switching memory device is provided, including an insulating layer having a top surface, a bottom electrode embedded in the insulating layer, a resistance switching layer disposed on the bottom electrode, and a top electrode formed on the resistance switching layer and covering the resistance switching layer. Also, the bottom electrode has an upper portion protruding from the top surface of the insulating layer, and the upper portion has round corners at edges.