公开(公告)号：US12008147B2

公开(公告)日：2024-06-11

申请号：US17520093

申请日：2021-11-05

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Paraskevas Bakopoulos ,  Ioannis (Giannis) Patronas ,  Dimitris Syrivelis ,  Liron Mula ,  Aviad Levy ,  Elad Mentovich

IPC: G06F21/72 ,  H04L9/08 ,  H04L9/40 ,  G06F21/85

CPC classification number: G06F21/72 ,  H04L9/0852 ,  H04L63/0435 ,  H04L63/061 ,  G06F21/85

Abstract: Devices, networking devices, and switches, among other things, are disclosed. An illustrative switch is disclosed to include a plurality of optical Input/Output (I/O) ports; a multi-chip module (MCM) assembly including switching circuitry and at least one chiplet that is optically coupled with one of the plurality of optical I/O ports; and a controller coupled with the at least one chiplet and configured to couple the at least one chiplet with a Quantum Key Distribution (QKD) device.

公开(公告)号：US11991159B2

公开(公告)日：2024-05-21

申请号：US17568582

申请日：2022-01-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Barak Gafni ,  Liron Mula

IPC: H04L9/40 ,  H04L12/46

CPC classification number: H04L63/0485 ,  H04L63/162 ,  H04L63/164 ,  H04L12/4633 ,  H04L63/0428

Abstract: Technologies for bi-directional encryption and decryption for underlay and overlay operations are described. One network device includes multiple ports, a network processing element, a programmable path-selection circuit, and a security IC. The programmable path-selection circuit is configured to operate in a first mode in which first outgoing packets are routed to the security integrated circuit to be encrypted before sending on one of the ports, and first incoming packets, received on one of the ports, are routed to the security integrated circuit to be decrypted. The programmable path-selection circuit is configured to operate in a second mode in which second incoming packets are routed to the security integrated circuit to be encrypted before processing by the network processing element and route second outgoing packets to the security integrated circuit to be decrypted after processing by the network processing element.

公开(公告)号：US11907754B2

公开(公告)日：2024-02-20

申请号：US17549949

申请日：2021-12-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Liron Mula ,  Natan Manevich

IPC: G06F9/48 ,  G06F1/08 ,  G06F13/16

CPC classification number: G06F9/4825 ,  G06F1/08 ,  G06F9/485 ,  G06F13/1689

Abstract: In one embodiment, a system includes a memory, a processing device including a device processor; and a device clock, and a peripheral device including an interface to share data with the processing device, a hardware clock, and processing circuitry to write respective interrupt signaling messages to the memory responsively to respective hardware clock values of the hardware clock, and wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to perform a time-dependent action.

公开(公告)号：US20230353664A1

公开(公告)日：2023-11-02

申请号：US18314834

申请日：2023-05-10

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gil Levy ,  Liron Mula ,  Barak Gafni

IPC: H04L69/22 ,  H04L69/324 ,  H04L69/323

CPC classification number: H04L69/22 ,  H04L69/324 ,  H04L69/323

Abstract: A parsing apparatus includes a packet-type identification circuit and a parser. The packet-type identification circuit is to receive a packet to be parsed, and to identify a packet type of the packet by extracting a packet-type identifier from a defined field in the packet. The parser is to store one or more parsing templates that specify parsing of one or more respective packet types. When the packet type of the packet corresponds to a parsing template among the stored parsing templates, the parser is to parse the packet in accordance with the stored parsing template. When the packet type of the packet does not correspond to any of the stored parsing templates, the parser is to parse the packet using an alternative parsing scheme.

公开(公告)号：US11656958B2

公开(公告)日：2023-05-23

申请号：US17244539

申请日：2021-04-29

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Liron Mula ,  Gil Levy ,  Itamar Rabenstein

IPC: G06F11/20 ,  G06F9/50 ,  G06F13/20

CPC classification number: G06F11/2007 ,  G06F9/5011 ,  G06F13/20 ,  G06F2201/85

Abstract: Methods, systems, and devices for redundant data bus inversion (DBI) sharing are described. A device may identify a group of channels included in a data bus. The device may determine whether the group of channels satisfies a criterion. Based on the determination, the device may allocate an overhead channel to the group of channels for a set of redundancy operations. Based on the determination, the device may allocate the overhead channel to the group of channels for a set of data bus inversion operations. The device may encode data associated with the group of channels based on the allocation of the overhead channel. The overhead channel may be included in the data bus.

公开(公告)号：US11588609B2

公开(公告)日：2023-02-21

申请号：US17148605

申请日：2021-01-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Liron Mula ,  Dotan David Levi ,  Ariel Almog

IPC: H04W40/20 ,  H04L7/00

Abstract: A network device includes one or more ports for connecting to a communication network, packet processing circuitry and clock circuitry. The packet processing circuitry is configured to communicate packets over the communication network via the ports. The clock circuitry includes a hardware clock configured to indicate a network time used for synchronizing network devices in the communication network, and a built-in accuracy test circuit configured to check an accuracy of the hardware clock.

公开(公告)号：US20230022037A1

公开(公告)日：2023-01-26

申请号：US17955591

申请日：2022-09-29

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Niv Aibester ,  Aviv Kfir ,  Gil Levy ,  Liron Mula ,  Barak Gafni

IPC: H04L49/90 ,  H04L43/0876 ,  H04L47/6275

Abstract: An apparatus for controlling a Shared Buffer (SB), the apparatus including an interface and a SB controller. The interface is to access flow-based data counts and admission states. The SB controller is to perform flow-based accounting of packets received by a network device coupled to a communication network, for producing flow-based data counts, each flow-based data count associated with one or more respective flows, and to generate admission states based at least on the flow-based data counts, each admission state being generated from one or more respective flow-based data counts.

公开(公告)号：US11552871B2

公开(公告)日：2023-01-10

申请号：US16900931

申请日：2020-06-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Ran Sela ,  Liron Mula ,  Ran Ravid ,  Guy Lederman ,  Dotan David Levi

IPC: H04L43/106 ,  H04J3/06 ,  H04L43/0852 ,  G06F15/173 ,  H04L7/00

Abstract: In one embodiment, a network device, includes a network interface port configured to receive data symbols from a network node over a packet data network, at least some of the symbols being included in data packets, and controller circuitry including physical layer (PHY) circuitry, which includes receive PHY pipeline circuitry configured to process the received data symbols, and a counter configured to maintain a counter value indicative of a number of the data symbols in the receive PHY pipeline circuitry.

公开(公告)号：US11336383B2

公开(公告)日：2022-05-17

申请号：US16910193

申请日：2020-06-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Liron Mula ,  Dotan David Levi ,  Ran Ravid ,  Guy Lederman

IPC: H04J3/06 ,  H04L12/46 ,  H04L43/0852 ,  H04L69/22

Abstract: In certain exemplary embodiments, a switching device is provided, including an input interface configured to communicate with a packet source, an output interface configured to communicate with a packet destination, and packet processing circuitry. The packet processing circuitry is configured to receive a plurality of packets from the packet source via the input interface, each of the plurality of packets being associated with a packet descriptor, at least one of the packet descriptors being a transmission time packet descriptor including a desired physical transmission time for the packet associated with the transmission time packet descriptor, to receive an indication of a clock time, and for each packet associated with a transmission time packet descriptor, to physically transmit the packet associated with the transmission time packet descriptor, via the output interface, at a clock time corresponding to the desired physical transmission time. Related apparatus an methods are also provided.

公开(公告)号：US11271874B2

公开(公告)日：2022-03-08

申请号：US16782075

申请日：2020-02-05

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis ,  Liron Mula

IPC: H04L12/861 ,  H04L49/90 ,  H04L45/745 ,  H04L69/22 ,  H04W56/00 ,  H04L29/06 ,  H04L47/10 ,  H04L12/46 ,  H04L49/00

Abstract: A network adapter includes a host interface configured to communicate with a host, a network interface configured to communicate with a communication network, and packet processing circuitry. The packet processing circuitry is configured to receive a packet from the host via the host interface, or from the communication network via the network interface, to receive an indication of a network time used for synchronizing network elements in the communication network, to match the packet to a rule, the rule including a condition and an action, and to perform the action in response to the packet meeting the condition, wherein one or more of (i) the condition in the rule and (ii) the action in the rule, depend on the network time.