公开(公告)号：US20080182343A1

公开(公告)日：2008-07-31

申请号：US11668553

申请日：2007-01-30

Applicant: Sachin Deshpande ,  Merritt Funk

Inventor： Sachin Deshpande ,  Merritt Funk

IPC: H01L21/00 ,  G01B11/02

CPC classification number: G01B11/06

Abstract: The invention can provide a method of processing a wafer using a Real-Time Parameter Tuning (RTPT) procedure to receive an input message that can include a pass-through message, a real-time feedforward message, or a real-time optimization message, or any combination thereof. The RTPT procedures can use real-time wafer temperature data to create, modify, and/or use measurement recipe data, measurement profile data, and/or measurement model data. In addition, RTPT procedures can use real-time wafer temperature data to create, modify, and/or use process recipe data, process profile data, and/or process model data.

Abstract translation: 本发明可以提供使用实时参数调整（RTPT）程序来处理晶片的方法，以接收可以包括直通消息，实时前馈消息或实时优化消息的输入消息， 或其任何组合。 RTPT程序可以使用实时晶片温度数据来创建，修改和/或使用测量配方数据，测量简档数据和/或测量模型数据。 此外，RTPT程序可以使用实时晶片温度数据来创建，修改和/或使用过程配方数据，过程配置文件数据和/或过程模型数据。

公开(公告)号：US07328418B2

公开(公告)日：2008-02-05

申请号：US11046903

申请日：2005-02-01

Applicant: Asao Yamashita ,  Merritt Funk ,  Daniel Prager

Inventor： Asao Yamashita ,  Merritt Funk ,  Daniel Prager

IPC: G06F17/50 ,  G06F9/45

CPC classification number: H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.

Abstract translation: 该方法包括用于蚀刻处理的方法，其允许调整隔离结构/嵌套结构/特征之间的偏置，校正其中隔离结构/特征需要小于嵌套结构/特征的过程，并且其中嵌套结构/特征 需要相对于孤立的结构/特征而减少，同时允许对修剪的关键控制。

公开(公告)号：US20080027577A1

公开(公告)日：2008-01-31

申请号：US11865739

申请日：2007-10-02

Applicant: David Horak ,  Wesley Natzle ,  Merritt Funk ,  Kevin Lally ,  Daniel Prager

Inventor： David Horak ,  Wesley Natzle ,  Merritt Funk ,  Kevin Lally ,  Daniel Prager

IPC: G06F19/00 ,  G01B11/14

CPC classification number: H01L22/20

Abstract: A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whether it is based on processing or metrology. Adjustments for wafer processing variation of previous process tools can be fed forward, and adjustments for the process and/or integrated metrology tools may be fed back automatically during the processing of semiconductor wafers. The invention implements process reference wafers to determine the origin in one mode, and measurement reference wafers to determine the origin of deviations in another mode.

Abstract translation: 公开了一种用于在半导体处理中校正特征尺寸与目标的偏差的系统，方法和程序产品。 本发明确定特征维度与目标维度的偏差的起源，而不管其是基于处理还是计量学。 可以向前馈送先前工艺工具的晶片处理变化的调整，并且可以在半导体晶片的处理期间自动地反馈过程和/或集成度量工具的调整。 本发明实施过程参考晶片以确定一种模式中的原点，以及测量参考晶片以确定另一种模式中偏差的起点。

公开(公告)号：US07305322B2

公开(公告)日：2007-12-04

申请号：US11396112

申请日：2006-03-31

Applicant: Merritt Funk ,  Daniel Prager

Inventor： Merritt Funk ,  Daniel Prager

IPC: G01B7/00 ,  G01B11/02

CPC classification number: G01R31/307 ,  G01R31/2846

Abstract: To determine the profile of an integrated circuit structure, a signal is measured off the structure with a metrology device. The measured signal is compared to signals in a virtual profile library. The comparison is stopped if matching criteria are met. A subset of a virtual profile data space is determined when the matching criteria are not met. The subset is determined using profile data space associated with the library. A virtual profile signal of the subset is selected. Virtual profile shape/parameters are determined based on the virtual profile signal. A difference is calculated between the measured and virtual profile signals. The difference is compared to virtual profile library creation criteria. If the criteria are met, then the structure is identified using virtual profile data, which includes the virtual profile shape/parameters, associated with the virtual profile signal. Or, if the criteria are not met, then a corrective action is applied.

Abstract translation: 为了确定集成电路结构的轮廓，使用测量装置测量结构的信号。 将测量的信号与虚拟简档库中的信号进行比较。 如果符合匹配条件，则比较停止。 当匹配条件不满足时确定虚拟简档数据空间的子集。 使用与库相关联的简档数据空间确定子集。 选择该子集的虚拟简档信号。 基于虚拟轮廓信号确定虚拟轮廓形状/参数。 在测量和虚拟简档信号之间计算差异。 将差异与虚拟简档库创建标准进行比较。 如果满足标准，则使用与虚拟简档信号相关联的虚拟简档数据（包括虚拟简档形状/参数）来识别结构。 或者，如果不符合标准，则应用纠正措施。

公开(公告)号：US20070239383A1

公开(公告)日：2007-10-11

申请号：US11394860

申请日：2006-03-31

Applicant: Merritt Funk ,  Daniel Prager

Inventor： Merritt Funk ,  Daniel Prager

IPC: G06F19/00

CPC classification number: G01N21/4788

Abstract: A method of refining a virtual profile library includes obtaining a reference signal measured off a reference structure on a semiconductor wafer with a metrology device. A best match is selected of the reference signal in a virtual profile data space. The virtual profile data space has data points with specified accuracy values. The data points represent virtual profile parameters and associated virtual profile signals. The virtual profile parameters characterize the profile of an integrated circuit structure. The best match being a data point of the profile data space with a signal closest to the reference signal. Refined virtual profile parameters are determined corresponding to the reference signal based on the virtual profile parameters of the selected virtual profile signal using a refinement procedure.

Abstract translation: 精细虚拟简档库的方法包括：使用测量装置获得在半导体晶片上的参考结构测量的参考信号。 在虚拟简档数据空间中选择参考信号的最佳匹配。 虚拟配置文件数据空间具有指定精度值的数据点。 数据点表示虚拟轮廓参数和相关联的虚拟轮廓信号。 虚拟轮廓参数表征集成电路结构的轮廓。 最佳匹配是具有最接近参考信号的信号的简档数据空间的数据点。 使用细化过程，基于所选虚拟简档信号的虚拟简档参数，对应于参考信号来确定精细虚拟简档参数。

公开(公告)号：US20070229806A1

公开(公告)日：2007-10-04

申请号：US11396210

申请日：2006-03-30

Applicant: Kevin Lally ,  Merritt Funk ,  Radha Sundararajan

Inventor： Kevin Lally ,  Merritt Funk ,  Radha Sundararajan

IPC: G01N21/00

CPC classification number: G01N21/9501 ,  G01N21/4788 ,  G01N21/95607 ,  H01L22/12

Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology includes directing an incident beam on the damaged structure. A diffracted beam is received from the damaged structure. The received diffracted beam is processed to determine a profile of an undamaged portion of the damaged structure and to measure an amount of dielectric damage of the damaged structure.

Abstract translation: 使用光学计量测量在半导体晶片上形成的损坏结构的方法包括将入射光束引导到损坏的结构上。 从损坏的结构接收衍射光束。 处理接收的衍射光束以确定受损结构的未损伤部分的轮廓并且测量损坏结构的电介质损伤的量。

公开(公告)号：US07158851B2

公开(公告)日：2007-01-02

申请号：US10609129

申请日：2003-06-30

Applicant: Merritt Funk

Inventor： Merritt Funk

IPC: G06F19/00

CPC classification number: G05B19/41875 ,  G05B2219/31265 ,  G05B2219/32195 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/22 ,  Y02P90/26

Abstract: A method of using a run-to-run (R2R) controller to provide wafer-to-wafer (W2W) control in a semiconductor processing system is provided. The R2R controller includes a feed-forward (FF) controller, a process model controller, a feedback (FB) controller, and a process controller. The R2R controller uses feed-forward data, modeling data, feedback data, and process data to update a process recipe on a wafer-to-wafer time frame.

Abstract translation: 提供了一种使用运行（R2R）控制器在半导体处理系统中提供晶圆到晶片（W2W）控制的方法。 R2R控制器包括前馈（FF）控制器，过程模型控制器，反馈（FB）控制器和过程控制器。 R2R控制器使用前馈数据，建模数据，反馈数据和过程数据来更新晶圆到晶片时间框架上的工艺配方。

公开(公告)号：US20060184264A1

公开(公告)日：2006-08-17

申请号：US11058321

申请日：2005-02-16

Applicant: James Willis ,  Merritt Funk ,  Kevin Lally ,  Kevin Pinto ,  Masayuki Tomoyasu ,  Raymond Peterson ,  Radha Sundararajan

Inventor： James Willis ,  Merritt Funk ,  Kevin Lally ,  Kevin Pinto ,  Masayuki Tomoyasu ,  Raymond Peterson ,  Radha Sundararajan

IPC: G06F19/00

CPC classification number: G05B19/4184 ,  G05B2219/31356 ,  G05B2219/32179 ,  G05B2219/45031 ,  Y02P80/40 ,  Y02P90/14 ,  Y02P90/20 ,  Y02P90/22 ,  Y02P90/86

Abstract: A method for implementing FDC in an APC system including receiving an FDC model from memory; providing the FDC model to a process model calculation engine; computing a vector of predicted dependent process parameters using the process model calculation engine; receiving a process recipe comprising a set of recipe parameters, providing the process recipe to a process module; executing the process recipe to produce a vector of measured dependent process parameters; calculating a difference between the vector of predicted dependent process parameters and the vector of measured dependent process parameters; comparing the difference to a threshold value; and declaring a fault condition when the difference is greater than the threshold value.

公开(公告)号：US20060042543A1

公开(公告)日：2006-03-02

申请号：US10927514

申请日：2004-08-27

Applicant: Merritt Funk ,  Wesley Natzle

Inventor： Merritt Funk ,  Wesley Natzle

IPC: B05C11/00

CPC classification number: H01L22/20 ,  G05B2219/45031

Abstract: The invention relates to controlling a semiconductor processing system. Among other things, the invention relates to a run-to-run controller to create virtual modules to control a multi-pass process performed by a multi-chamber tool during the processing of a semiconductor wafer.

Abstract translation: 本发明涉及控制半导体处理系统。 其中，本发明涉及一种运行到运行的控制器，用于创建虚拟模块以控制在半导体晶片的处理期间由多室工具执行的多遍处理。

公开(公告)号：US10395903B2

公开(公告)日：2019-08-27

申请号：US15983532

申请日：2018-05-18

Applicant: Zhiying Chen ,  Lee Chen ,  Merritt Funk

Inventor： Zhiying Chen ,  Lee Chen ,  Merritt Funk

IPC: H01J37/32 ,  C23C16/50 ,  H01J37/30

Abstract: A processing system is disclosed, having an electron beam source chamber that excites plasma to generate an electron beam, and an ion beam source chamber that houses a substrate and also excites plasma to generate an ion beam. The processing system also includes a dielectric injector coupling the electron beam source chamber to the ion beam source chamber that simultaneously injects the electron beam and the ion beam and propels the electron beam and the ion beam in opposite directions. The voltage potential gradient between the electron beam source chamber and the ion beam source chamber generates an energy field that is sufficient to maintain the electron beam and ion beam as a plasma treats the substrate so that radio frequency (RF) power initially applied to the processing system to generate the electron beam can be terminated thus improving the power efficiency of the processing system.