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78 条记录 (耗时 0.043 秒)

    Group based codes for multi-dimensional recording (MDR)
    61.
    发明授权
    Group based codes for multi-dimensional recording (MDR) 有权
    用于多维记录（MDR）的基于组的代码

    公开(公告)号：US09396062B1

    公开(公告)日：2016-07-19

    申请号：US14245886

    申请日：2014-04-04

    申请人： Deepak Sridhara ,  William Radich ,  Ara Patapoutian ,  Timothy R Feldman ,  Mark Gaertner

    发明人： Deepak Sridhara ,  William Radich ,  Ara Patapoutian ,  Timothy R Feldman ,  Mark Gaertner

    IPC分类号： G11C29/00 ,  G06F11/10

    CPC分类号： G06F11/1044 ,  G06F11/1008 ,  G06F11/1068

    摘要： A multi-dimensional recording (MDR) system may include a group based coding circuit (GBCC) which can implement error correcting codes via outer codes. The GBCC can implement outer codes, including interleaving outer codes, in MDR systems where inner codewords include multiple memory groupings. The multiple memory groupings may be across different structural divisions within a data storage medium; or could be across multiple different data storage mediums.

    摘要翻译： 多维记录（MDR）系统可以包括基于组的编码电路（GBCC），其可以通过外部代码实现纠错码。 GBCC可以在其中内部码字包括多个存储器分组的MDR系统中实现外部代码，包括交织外部代码。 多个存储器分组可以跨数据存储介质中的不同结构划分; 或者可以跨越多个不同的数据存储介质。

    Multiuse data channel
    62.
    发明授权
    Multiuse data channel 有权
    多用数据通道

    公开(公告)号：US09130596B2

    公开(公告)日：2015-09-08

    申请号：US13172457

    申请日：2011-06-29

    申请人： Ara Patapoutian ,  Hieu V. Nguyen ,  Prafulla Bollampalli Reddy

    发明人： Ara Patapoutian ,  Hieu V. Nguyen ,  Prafulla Bollampalli Reddy

    IPC分类号： H03M13/29 ,  H03M13/00 ,  H03M13/09 ,  H03M13/11 ,  H03M13/15

    CPC分类号： H04L1/0045 ,  G06F11/1072 ,  G11C29/52 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/2906 ,  H03M13/6516 ,  H03M13/6561

    摘要： Presented is a data channel with selectable components, such as encoders or decoders. Also, data having different data signal characteristics can be processed through a data channel based on the data signal characteristics. Further, a data channel may have independent encoding path and an independent decoding path. For example, a first data transmission having first data signal characteristics may be processed via a data channel based on a first selected set of components of the data channel and a second data transmission having second data signal characteristics different than the first data signal characteristics may be processed via the data channel using a second selected set of components in the data channel. The first selected set of components may be different than the second selected set of components, but may share one or more common components.

    摘要翻译： 提出了具有可选组件的数据通道，例如编码器或解码器。 此外，可以基于数据信号特性通过数据信道来处理具有不同数据信号特性的数据。 此外，数据信道可以具有独立的编码路径和独立的解码路径。 例如，具有第一数据信号特性的第一数据传输可以经由数据信道基于数据信道的第一选定组件集合进行处理，并且具有与第一数据信号特性不同的第二数据信号特性的第二数据传输可以是 通过数据信道使用数据信道中的第二组选择的组来处理。 第一选择的组件集合可以不同于第二选择的组件集合，但是可以共享一个或多个公共组件。

    Determination of memory read reference and programming voltages
    63.
    发明授权
    Determination of memory read reference and programming voltages 有权
    存储器读取参考和编程电压的确定

    公开(公告)号：US08760932B2

    公开(公告)日：2014-06-24

    申请号：US13275497

    申请日：2011-10-18

    申请人： Arvind Sridharan ,  Ara Patapoutian

    发明人： Arvind Sridharan ,  Ara Patapoutian

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/28 ,  G11C16/3418

    摘要： Symmetrical or asymmetrical noise distributions for voltages corresponding to symbols that can be stored in multi-level memory cells (MLCs) of a memory device are used to determine read reference and/or programming voltages. The read reference voltages and/or programming voltages for the MLCs are jointly determined using the symmetrical distributions and a maximum likelihood estimation (MLE) and/or by determining at least one of the read reference voltages and the programming voltages using the asymmetrical distributions.

    摘要翻译： 用于对应于可存储在存储器件的多级存储器单元（MLC）中的符号的电压的对称或非对称噪声分布用于确定读取参考和/或编程电压。 使用对称分布和最大似然估计（MLE）和/或通过使用不对称分布确定读取的参考电压和编程电压中的至少一个来共同确定MLC的读取参考电压和/或编程电压。

    Shifting cell voltage based on grouping of solid-state, non-volatile memory cells
    64.
    发明授权
    Shifting cell voltage based on grouping of solid-state, non-volatile memory cells 有权
    基于固态，非易失性存储单元的分组来移动电池电压

    公开(公告)号：US08737133B2

    公开(公告)日：2014-05-27

    申请号：US13275675

    申请日：2011-10-18

    申请人： Arvind Sridharan ,  Ara Patapoutian

    发明人： Arvind Sridharan ,  Ara Patapoutian

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/28 ,  G11C16/349 ,  G11C29/00

    摘要： Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells.

    摘要翻译： 将固态非易失性存储器的单元分配给多个组中的一个。 鉴于从单元读取的实际符号，每个组由存储在单元中的预期符号定义。 基于组内的单元计数，可以确定参考电压的偏移将降低单元的集合误码率。 该移位可以应用于影响单元的数据访问操作。

    Outer code protection for solid state memory devices
    65.
    发明授权
    Outer code protection for solid state memory devices 有权
    固态存储器件的外部代码保护

    公开(公告)号：US08572457B2

    公开(公告)日：2013-10-29

    申请号：US12790120

    申请日：2010-05-28

    申请人： Bernardo Rub ,  Ara Patapoutian ,  Arvind Sridharan ,  Bruce D. Buch

    发明人： Bernardo Rub ,  Ara Patapoutian ,  Arvind Sridharan ,  Bruce D. Buch

    IPC分类号： H03M13/00 ,  G11C29/00 ,  G06F11/00

    CPC分类号： G06F11/1012

    摘要： Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data.

    摘要翻译： 外码字可以跨越存储器设备的多个数据块，多个芯片或多个芯片，以防止存储在块，芯片和/或芯片中的数据中的错误。 固态存储器件被布置在多个数据块中，每个块包括以多页布置的存储器单元的阵列。 数据被编码成内码字和基于符号的外码字。 内码字和基于符号的外码字被存储在多个块的存储单元中。 一个或多个内部码字被存储在每个块的每个页面中，并且每个外部码字的一个或多个符号被存储在每个块的至少一个页面中。 内部码字和外部码字从存储器件读取并用于校正数据中的错误。

    CATEGORIZING BIT ERRORS OF SOLID-STATE, NON-VOLATILE MEMORY
    66.
    发明申请
    CATEGORIZING BIT ERRORS OF SOLID-STATE, NON-VOLATILE MEMORY 有权
    分类固态，非易失性存储器的位错误

    公开(公告)号：US20130094288A1

    公开(公告)日：2013-04-18

    申请号：US13275418

    申请日：2011-10-18

    申请人： Ara Patapoutian ,  Arvind Sridharan

    发明人： Ara Patapoutian ,  Arvind Sridharan

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/06 ,  G11C16/3454

    摘要： Bit errors affecting cells of a solid-state, non-volatile memory are assigned to at least a first or a second category based on a relative amount of voltage shift that caused the respective bit errors in the respective cells. A reference voltage used to access the respective cells is adjusted to manage the respective bit errors of the first category. Additional corrective measures are taken to manage the respective bit errors of the second category.

    摘要翻译： 基于导致各个单元中的各个位错误的电压偏移的相对量，将影响固态非易失性存储器的单元的位错误分配给至少第一或第二类别。 调整用于访问相应单元的参考电压以管理第一类别的相应位错误。 采取额外的纠正措施来管理第二类别的相应位错误。

    Programmable soft-output Viterbi algorithm system and method
    67.
    发明授权
    Programmable soft-output Viterbi algorithm system and method 有权
    可编程软输出维特比算法系统及方法

    公开(公告)号：US08307267B2

    公开(公告)日：2012-11-06

    申请号：US12048830

    申请日：2008-03-14

    申请人： Raman Venkataramani ,  Alexander Kuznetsov ,  Ara Patapoutian

    发明人： Raman Venkataramani ,  Alexander Kuznetsov ,  Ara Patapoutian

    IPC分类号： H03M13/03

    CPC分类号： G11B20/10009 ,  G11B20/10287 ,  G11B20/10296 ,  G11B2220/2516

    摘要： In a particular embodiment, a channel detector is disclosed that includes a programmable look-up table (LUT) to relate user bits to channel bits. The programmable LUT is adapted to be implemented on a state trellis of arbitrary radix. The channel detector further includes a sectional precoder coupled to a channel and having access to the programmable LUT. The sectional precoder is adapted to map channel bits to user bits and vice versa using a programmable LUT.

    摘要翻译： 在特定实施例中，公开了一种信道检测器，其包括用于将用户比特与信道比特相关联的可编程查找表（LUT）。 可编程LUT适于在任意基数的状态网格上实现。 信道检测器还包括耦合到信道并且访问可编程LUT的分段预编码器。 分段预编码器适于使用可编程LUT将通道位映射到用户位，反之亦然。

    Iterating Inner and Outer Codes for Data Recovery
    68.
    发明申请
    Iterating Inner and Outer Codes for Data Recovery 有权
    迭代内部和外部代码进行数据恢复

    公开(公告)号：US20120278679A1

    公开(公告)日：2012-11-01

    申请号：US13094048

    申请日：2011-04-26

    申请人： Bernardo Rub ,  Ara Patapoutian ,  Arvind Sridharan ,  Bruce D. Buch

    发明人： Bernardo Rub ,  Ara Patapoutian ,  Arvind Sridharan ,  Bruce D. Buch

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G11B20/1833 ,  G11B2020/1836 ,  G11B2020/1853 ,  G11B2220/2516 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/2909 ,  H03M13/2927 ,  H03M13/3746

    摘要： A storage medium includes at least one data unit defining a plurality of symbol-based inner code words and a plurality of symbol-based outer code words. Each symbol included in one of the inner code words is also included in one of the outer code words. A processor is configured to perform a first iteration of inner code error correction on the plurality of symbol-based inner code words, a first iteration of outer code error correction on the plurality of symbol-based outer code words and a second iteration of inner code error correction on the plurality of symbol-based inner code words. In the first iteration of outer code error corrections, at least one of the outer code words is correctable. In the second iteration of inner code error correction, at least one of the inner code words is correctable.

    摘要翻译： 存储介质包括定义多个基于符号的内码字和多个基于符号的外码字的至少一个数据单元。 包含在其中一个内部码字中的每个符号也被包括在一个外部码字中。 处理器被配置为对所述多个基于符号的内码字执行内码纠错的第一迭代，对所述多个基于符号的外码字进行外码纠错的第一迭代和内码的第二次迭代 对多个基于符号的内码字进行纠错。 在外码错误校正的第一次迭代中，外码字中的至少一个是可校正的。 在内码纠错的第二次迭代中，内码字中的至少一个是可校正的。

    Reuse of information from memory read operations
    69.
    发明授权
    Reuse of information from memory read operations 有权
    从内存读取操作重新使用信息

    公开(公告)号：US08243511B2

    公开(公告)日：2012-08-14

    申请号：US12891475

    申请日：2010-09-27

    申请人： Ara Patapoutian ,  Bernardo Rub ,  Bruce D. Buch

    发明人： Ara Patapoutian ,  Bernardo Rub ,  Bruce D. Buch

    IPC分类号： G11C16/08 ,  G11C16/28

    CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3418

    摘要： A nominal reference read operation compares analog voltages of the memory cells to at least one nominal reference voltage. A shifted reference read operation compares the analog voltages of the memory cells to at least one shifted reference voltage that is shifted from the nominal reference voltage to compensate for an expected change in the analog voltages of the memory cells. Data stored in the memory cells is decoded by a first decoding process that uses the information from either the nominal reference read operation or the shifted reference read operation. The data stored in the memory cells is decoded by a second decoding process that uses the information from both the nominal reference read operation and the shifted reference read operation.

    摘要翻译： 标称参考读取操作将存储器单元的模拟电压与至少一个标称参考电压进行比较。 移位的参考读取操作将存储器单元的模拟电压与从标称参考电压偏移的至少一个移位的参考电压进行比较，以补偿存储器单元的模拟电压的预期变化。 通过使用来自标称参考读取操作或移位参考读取操作的信息的第一解码处理对存储单元中存储的数据进行解码。 通过使用来自标称参考读取操作和偏移的参考读取操作的信息的第二解码处理来对存储单元中存储的数据进行解码。