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    Cache release command for cache reads in a memory sub-system
    61.
    发明授权
    Cache release command for cache reads in a memory sub-system 有权

    公开(公告)号：US11188473B1

    公开(公告)日：2021-11-30

    申请号：US16949512

    申请日：2020-10-30

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Yoav Weinberg

    IPC: G06F12/00 ,  G06F12/0882 ,  G06F12/0817 ,  G06F9/30 ,  G06F12/0891

    Abstract: A memory device includes a page cache comprising a cache register, a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a first cache read command requesting first data from the memory array spread across the plurality of memory planes, and returns, to the requestor, data associated with a first subset of the plurality of memory planes and pertaining to a previous read command, while concurrently copying data associated with a second subset of the plurality of memory planes and pertaining to the previous read command into the cache register. The control logic further receives, from the requestor, a cache release command, and returns, to the requestor, the data associated with the second subset of the plurality of memory planes and pertaining to the previous read command, while concurrently copying data associated with the first subset of the plurality of memory planes and pertaining to the first cache read command into the cache register.

    SEMICONDUCTOR DEVICE STRUCTURES, SEMICONDUCTOR DEVICES, AND ELECTRONIC SYSTEMS
    62.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURES, SEMICONDUCTOR DEVICES, AND ELECTRONIC SYSTEMS 审中-公开

    公开(公告)号：US20200066746A1

    公开(公告)日：2020-02-27

    申请号：US16106752

    申请日：2018-08-21

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee

    IPC: H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  G11C11/4097 ,  G11C11/419

    Abstract: A semiconductor device structure comprises blocks having substantially uniform pitch laterally-extending throughout a first region, a second region laterally-neighboring the first memory region, and a third region laterally-neighboring the second region; memory strings longitudinally-extending through a first portion of the blocks located in the first region; pillar structures longitudinally-extending through a second portion of the blocks located in the second region; conductive contacts longitudinally-extending through a third portion of the blocks located in the third region; and conductive line structures electrically coupled to and laterally-extending between the memory strings and the conductive contacts. Each of the blocks comprises tiers, each tier comprising a conductive structure and an insulating structure longitudinally-neighboring the conductive structure. Semiconductor devices and electronic systems are also described.

    Data burst queue management
    65.
    发明授权
    Data burst queue management 有权

    公开(公告)号：US12248411B2

    公开(公告)日：2025-03-11

    申请号：US18144957

    申请日：2023-05-09

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Luigi Pilolli ,  Ali Feiz Zarrin Ghalam ,  Xiangyu Tang ,  Daniel Jerre Hubbard

    IPC: G06F13/16 ,  G06F12/0879 ,  G06F13/32

    Abstract: Operations include establishing a queue storing a list of data burst commands to be communicated via a multiplexed interface coupled to the set of memory dies, communicating, during a first time period, a first data burst command in the queue to a first memory die of the set of memory dies via the multiplexed interface, and communicating, during a second time period, a second data burst command in the queue to a second memory die of the set of memory dies via the multiplexed interface, where a first latency associated with the first data burst command occurs during the second time period.

    MULTIPLE WRITE PROGRAMMING FOR A SEGMENT OF A MEMORY DEVICE
    66.
    发明申请
    MULTIPLE WRITE PROGRAMMING FOR A SEGMENT OF A MEMORY DEVICE 有权

    公开(公告)号：US20250077416A1

    公开(公告)日：2025-03-06

    申请号：US18781838

    申请日：2024-07-23

    Applicant: Micron Technology, Inc.

    Inventor： Huai-Yuan Tseng ,  Xiangyu Tang ,  Eric N. Lee ,  Haibo Li ,  Kishore Kumar Muchherla ,  Akira Goda

    IPC: G06F12/02

    Abstract: A memory device can include a memory array including memory cells arranged in one or more pages. The memory array can be coupled to control logic to receive a first request to write first data to a page of the one or more pages and program the first data to the page of the one or more pages at a first time responsive to receiving the first request. The control logic is further to receive a second request to write second data to the page of the one or more pages, read the page of the one or more pages, and program the second data to the page of the one or more pages at a second time responsive to receiving the second request. The control logic can also receive an erase request to erase the one or more pages after the second time.

    Data burst suspend mode using pause detection
    67.
    发明授权
    Data burst suspend mode using pause detection 有权

    公开(公告)号：US12182046B2

    公开(公告)日：2024-12-31

    申请号：US18119578

    申请日：2023-03-09

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Leonid Minz ,  Yoav Weinberg ,  Ali Feiz Zarrin Ghalam ,  Luigi Pilolli

    IPC: G06F13/30 ,  G06F13/16

    Abstract: Operations include monitoring a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal, determining whether a period of time during which the logical level of the first pin is held at a first logical level satisfies a threshold condition, in response to determining that the period of time satisfies the threshold condition, continuing to monitor the logical level of the first pin, determining whether the logical level of the first pin changed from the first logical level to a second logical level, and in response to determining that the logical level of the first pin changed from the first logical to the second logical level, causing warmup cycles to be performed.

    Memory devices for multiple read operations
    68.
    发明授权
    Memory devices for multiple read operations 有权

    公开(公告)号：US12142343B2

    公开(公告)日：2024-11-12

    申请号：US18232949

    申请日：2023-08-11

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Eric N. Lee ,  Kishore Kumar Muchherla ,  Jeffrey S. McNeil ,  Jung-Sheng Hoei

    IPC: G11C16/06 ,  G11C7/10 ,  G11C7/14 ,  G11C7/22

    Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.

    WORKLOAD-BASED SCAN OPTIMIZATION
    70.
    发明公开
    WORKLOAD-BASED SCAN OPTIMIZATION 审中-公开

    公开(公告)号：US20240248646A1

    公开(公告)日：2024-07-25

    申请号：US18623881

    申请日：2024-04-01

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Jonathan S. Parry ,  Lakshmi Kalpana Vakati

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679

    Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.

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