公开(公告)号：US20220013173A1

公开(公告)日：2022-01-13

申请号：US17443203

申请日：2021-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Innocenzo Tortorelli ,  Stephen Tang ,  Christina Papagianni

IPC: G11C13/00 ,  G11C11/56

Abstract: Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

公开(公告)号：US20210366541A1

公开(公告)日：2021-11-25

申请号：US17331610

申请日：2021-05-26

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Agostino Pirovano ,  Innocenzo Tortorelli

IPC: G11C13/00

Abstract: Methods, systems, and devices for operating memory cell(s) are described. A resistance of a storage element included in a memory cell may be programmed by applying a voltage to the memory cell that causes ion movement within the storage element, where the storage element remains in a single phase and has different resistivity based on a location of the ions within the storage element. In some cases, multiple of such storage elements may be included in a memory cell, where ions within the storage elements respond differently to electric pulses, and a non-binary logic value may be stored in the memory cell by applying a series of voltages or currents to the memory cell.

公开(公告)号：US11158358B2

公开(公告)日：2021-10-26

申请号：US16518876

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Richard K. Dodge ,  Innocenzo Tortorelli ,  Mattia Robustelli ,  Mario Allegra

IPC: G11C7/10

Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).

公开(公告)号：US11152065B2

公开(公告)日：2021-10-19

申请号：US16863175

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Andrea Redaelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Mario Allegra ,  Paolo Fantini

IPC: G11C13/02 ,  G11C13/00 ,  G11C11/56 ,  H01L27/24 ,  H01L45/00

Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

公开(公告)号：US11037613B2

公开(公告)日：2021-06-15

申请号：US16514431

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Anna Maria Conti ,  Mattia Robustelli ,  Innocenzo Tortorelli ,  Mario Allegra

IPC: G11C7/22 ,  G11C11/16

Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.

公开(公告)号：US20210165577A1

公开(公告)日：2021-06-03

申请号：US17175155

申请日：2021-02-12

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Innocenzo Tortorelli

IPC: G06F3/06 ,  G11C7/08 ,  G11C7/22 ,  G11C8/12 ,  G11C13/00 ,  G11C16/34

Abstract: The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can perform sensing operations on an array of memory cells by applying a first signal to a first portion of the array of memory cells and a second signal to a second portion of the array of memory cells.

公开(公告)号：US11018300B2

公开(公告)日：2021-05-25

申请号：US16665955

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Andrea Redaelli ,  Innocenzo Tortorelli

IPC: H01L45/00 ,  H01L27/24

Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.

公开(公告)号：US10985212B2

公开(公告)日：2021-04-20

申请号：US16385636

申请日：2019-04-16

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli

IPC: G11C13/00 ,  G11C11/56 ,  G11C7/00 ,  H01L23/528 ,  H01L27/24 ,  H01L45/00

Abstract: Methods, systems, and devices for multi-component cell architectures for a memory device are described. A memory device may include self-selecting memory cells that include multiple self-selecting memory components (e.g., multiple layers or other segments of a self-selecting memory material, separated by electrodes). The multiple self-selecting memory components may be configured to collectively store one logic state based on the polarity of a programming pulse applied to the memory cell. The multiple memory component layers may be collectively (concurrently) programmed and read. The multiple self-selecting memory components may increase the size of a read window of the memory cell when compared to a memory cell with a single self-selecting memory component. The read window for the memory cell may correspond to the sum of the read windows of each self-selecting memory component.

公开(公告)号：US10937829B2

公开(公告)日：2021-03-02

申请号：US16550532

申请日：2019-08-26

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Andrea Redaelli ,  Fabio Pellizzer ,  Innocenzo Tortorelli

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/115

Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.

公开(公告)号：US10921989B2

公开(公告)日：2021-02-16

申请号：US15683821

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Innocenzo Tortorelli

IPC: G11C16/16 ,  G06F3/06 ,  G11C7/22 ,  G11C16/34 ,  G11C7/08 ,  G11C13/00 ,  G11C8/12

Abstract: The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can perform sensing operations on an array of memory cells by applying a first signal to a first portion of the array of memory cells and a second signal to a second portion of the array of memory cells.