公开(公告)号：US10460981B2

公开(公告)日：2019-10-29

申请号：US16183493

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Anna Maria Conti ,  Sara Vigano

IPC: H01L27/11551 ,  H01L21/762 ,  H01L29/78 ,  H01L29/744 ,  H01L21/308 ,  H01L21/8249 ,  H01L29/66 ,  H01L21/8239 ,  H01L27/102 ,  H01L21/8229 ,  H01L21/8234 ,  H01L27/105 ,  H01L29/423 ,  H01L29/749

Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

公开(公告)号：US20190036022A1

公开(公告)日：2019-01-31

申请号：US15660829

申请日：2017-07-26

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Andrea Redaelli ,  Innocenzo Tortorelli

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1675 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/141

Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.

公开(公告)号：US09343149B2

公开(公告)日：2016-05-17

申请号：US14328536

申请日：2014-07-10

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Davide Fugazza ,  Johannes A. Kalb

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0004 ,  G11C7/04 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/0092

Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.

Abstract translation: 本文公开的各种实施例包括用于将存储器阵列的相变存储器（PCM）单元放置在其中在应用随后的SET编程信号之前增强PCM单元的成核概率的温度状态的方法和装置。 在一个实施例中，该方法包括将成核信号施加到PCM单元以在存储器阵列内形成成核位置，其中成核信号具有非零上升沿。 随后施加编程信号以在所述多个PCM单元的选定的单元内实现期望的结晶度。 还描述了附加的方法和装置。

公开(公告)号：US08634242B2

公开(公告)日：2014-01-21

申请号：US13720045

申请日：2012-12-19

Applicant: Micron Technology, Inc.

Inventor： Alessandro Grossi ,  Giulio Albini ,  Anna Maria Conti

IPC: G11C16/00

CPC classification number: H01L21/768 ,  H01L23/48 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  H01L27/11578 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Subject matter disclosed herein relates to a multi-level flash memory and a process flow to form same.

Abstract translation: 本文公开的主题涉及多级闪存和形成其的处理流程。

公开(公告)号：US20130147045A1

公开(公告)日：2013-06-13

申请号：US13720045

申请日：2012-12-19

Applicant: Micron Technology, Inc.

Inventor： Alessandro Grossi ,  Giulio Albini ,  Anna Maria Conti

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/768 ,  H01L23/48 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  H01L27/11578 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Subject matter disclosed herein relates to a multi-level flash memory and a process flow to form same.

Abstract translation: 本文公开的主题涉及多级闪存和形成其的处理流程。