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公开(公告)号：US11983433B2
公开(公告)日：2024-05-14
申请号：US17505056
申请日：2021-10-19
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer
CPC classification number: G06F3/0655 , G06F3/061 , G06F3/0679
Abstract: Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may receive an access command transmitted to the memory device via a bus. The memory device may transmit data requested by the access command over data lines and a control signal that indicates the bus is in an active state over a control line. The control signal may be transmitted during a first unit interval of a read operation. The control signal may be configured to have a first voltage when the bus is in an idle state and a second voltage when the bus is in the active state. The control line may be configured to have or trend toward the first voltage when the bus is in the idle state.
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公开(公告)号：US20240120947A1
公开(公告)日：2024-04-11
申请号：US17961805
申请日：2022-10-07
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Scott E. Schaefer
CPC classification number: H03M13/159 , H03M13/1105 , H03M13/611
Abstract: Methods, systems, and devices for error detection and classification at a host device are described. A host device may communicate a read command for a codeword stored at a memory device. In response to communicating the read command, the host device may receive the codeword and an error indication bit that indicates whether the memory device detected an error in the codeword. The host device may use the codeword to generate a set of syndrome bits. The host device may determine an error status of the codeword based on the error indication bit for the codeword and the set of syndrome bits for the codeword.
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公开(公告)号：US20240118961A1
公开(公告)日：2024-04-11
申请号：US17938898
申请日：2022-10-07
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Scott E. Schaefer
CPC classification number: G06F11/0772 , G06F11/0793 , G06F11/1068
Abstract: Methods, systems, and devices for error detection and classification are described. A memory device may read a codeword from a memory and generate a first set of syndrome bits for the codeword. The memory device may use the first set of syndrome bits to generate a first error detection bit. The memory device may generate a second set of syndrome bits for the codeword and use the second set of syndrome bits to generate a second error detection bit. The memory device may provide the first error detection bit and the second error detection bit to a host device.
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公开(公告)号：US20240103966A1
公开(公告)日：2024-03-28
申请号：US17934452
申请日：2022-09-22
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
CPC classification number: G06F11/1068 , G06F11/0772 , G06F11/0793
Abstract: Methods, systems, and devices for redundancy-based error detection in a memory device are described. A memory device may read multiple copies of a codeword from memory and generate for each codeword copy an error detection bit that indicates whether the memory device detected an error in that codeword. Additionally, the memory device may compare the codeword copies and generate one or more match bits that indicate whether corresponding portions of the codewords match. Using a combination of the error detection bits and the match bits, the memory device may determine the error status of each codeword.
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公开(公告)号：US11928333B2
公开(公告)日：2024-03-12
申请号：US17946183
申请日：2022-09-16
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
IPC: G06F3/06 , G11C7/20 , G11C11/4072
CPC classification number: G06F3/0604 , G06F3/0655 , G06F3/0679 , G11C7/20 , G11C11/4072
Abstract: Methods, systems, and devices for reset verification in a memory system are described. In some examples, a memory device may perform a reset operation and set a mode register to a first value based on performing the reset operation. The first value may be associated with a successful execution of the reset command. The memory device may transmit an indication to a host device based on determining the first value. The host device may determine from the received indication or from the first value stored in the mode register that the first value is associated with the successful execution of the reset command. Thus, the memory device, or the host device, or both may be configured to verify whether the reset operation is successful.
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Patent Agency Ranking
公开(公告)号：US11928018B2
公开(公告)日：2024-03-12
申请号：US17889203
申请日：2022-08-16
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
CPC classification number: G06F11/0793 , G06F11/073 , G06F11/1048
Abstract: Methods, systems, and devices for coordinated error protection are described. A set of data and an indication of whether a first management procedure performed by a memory device on the set of data detected one or more errors in the set of data may be received at a host device. At the host device, a second error management procedure may be performed on the set of data received from the memory device. Based on the received indication and the second error management procedure, multiple bits indicating whether one or more errors associated with the set of data were detected at the memory device, the host device, or both may be generated. The set of data may be validated or discarded based on the multiple bits.
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公开(公告)号：US11816339B2
公开(公告)日：2023-11-14
申请号：US17391898
申请日：2021-08-02
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0655 , G06F3/0679
Abstract: Methods, systems, and devices for selectable error control for memory device are described. An apparatus may include a memory array and a circuit configurable to perform a first error control operation and a second error control operation on data stored by the memory array. The circuit may include a first plurality of gates enabled during the first error control operation and configured to generate a first set of bits associated with a first matrix of the first error control operation. The circuit may also include a second plurality of gates enabled during the second error control operation and configured to generate a second set of bits associated with the second matrix of the second error control operation. The circuit may further include a third plurality of gates configured to generate a third set of bits that are common to both the first matrix and the second matrix.
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公开(公告)号：US11714576B2
公开(公告)日：2023-08-01
申请号：US17505046
申请日：2021-10-19
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Melissa I. Uribe
CPC classification number: G06F3/0659 , G06F3/0614 , G06F3/0679 , G06F13/1668 , G06F2213/16
Abstract: Methods, systems, and devices for memory bus drive defect detection and related operations are described. A controller coupled with a memory array may receive a command for data. The memory array may include one or more pins for communicating data to and from the memory array, in response to the command. The controller may transmit to the memory array, over a bus that is coupled with the controller and the pins, the command. The controller may detect, based at least in part on a resistor coupled with the bus and a power supply of the memory array, that the bus is operating in a first state after transmitting the command. The first state may comprise a voltage that is relatively higher than a voltage of the second state. The controller may determine a defect associated with the bus or the pin based on detecting the bus in the first state.
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公开(公告)号：US20230141845A1
公开(公告)日：2023-05-11
申请号：US18093762
申请日：2023-01-05
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Todd Jackson Plum , Mark D. Ingram , Scott E. Schaefer , Scott D. Van De Graaff
CPC classification number: G06F12/023 , G06F11/3495 , G06F2212/7211
Abstract: Methods, systems, and devices for adaptive user defined health indications are described. A host device may be configured to dynamically indicate adaptive health flags for monitoring health and wear information for a memory device. The host device may indicate, to a memory device, a first index. The first index may correspond to a first level of wear of a set of multiple indexed levels of wear for the memory device. The memory device may determine that a metric of the memory device satisfies the first level of wear and indicate, to the host device, that the first level of wear is satisfied. The host device may receive the indication that the first level of wear is satisfied and indicate, to the memory device, a second level of wear of the set of indexed levels of wear that is different than the first level of wear.
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公开(公告)号：US20230072766A1
公开(公告)日：2023-03-09
申请号：US17889982
申请日：2022-08-17
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer
IPC: G06F11/07
Abstract: Methods, systems, and devices for error log indication via error control information are described. For instance, a memory device may transmit, to a host device, a first signal including a set of error control bits indicating that an error log of the memory device includes information for use by the host device. The memory device may receive, from the host device in response to the first signal, a second signal including a request to retrieve the information of the error log. The memory device may transmit, to the host device in response to the second signal, a third signal including the information of the error log.
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