公开(公告)号：US20190180191A1

公开(公告)日：2019-06-13

申请号：US16280872

申请日：2019-02-20

Applicant: Micron Technology, Inc.

Inventor： Paul D. Dlugosch ,  Harold B Noyes

IPC: G06N5/02 ,  H04L29/06

Abstract: Methods and apparatus are provided involving adaptive content inspection. In one embodiment, a content inspection processor may identify information with respect to input data and provide the information to a host controller. The host controller may adapt search criteria or other parameters and provide the adapted parameter to the content inspection processor. Other embodiments may include a content inspection processor having integrated feedback, such that results data is fed back to the content inspection processor. The results data may be processed before being provided to the content inspection processor.

公开(公告)号：US10157208B2

公开(公告)日：2018-12-18

申请号：US15357593

申请日：2016-11-21

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06F17/30 ,  G06F1/32 ,  G06K9/00

Abstract: Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.

公开(公告)号：US20180322006A1

公开(公告)日：2018-11-08

申请号：US16030479

申请日：2018-07-09

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G06F11/10 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/1076 ,  H03M13/09

Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.

公开(公告)号：US20180307463A1

公开(公告)日：2018-10-25

申请号：US16017387

申请日：2018-06-25

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes

IPC: G06F7/02 ,  G06F5/06

CPC classification number: G06F7/02 ,  G06F5/06 ,  G06F2207/025

Abstract: Systems and methods are provided, such as those that enable identification of data flows and corresponding results in a pattern-recognition processor. In one embodiment, a system may include the pattern-recognition processor and a flow identification register, wherein a unique flow identifier for each data flow is stored in the register. The system may include a results buffer that stores the results data and the flow identifier for each data flow, so that the results data may be related to a specific data flow.

公开(公告)号：US10067901B2

公开(公告)日：2018-09-04

申请号：US15683649

申请日：2017-08-22

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes ,  Inderjit S. Bains

IPC: G06F17/00 ,  G06F13/40 ,  G06F15/78 ,  G06F9/448 ,  G06N3/08

Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.

公开(公告)号：US20180032456A1

公开(公告)日：2018-02-01

申请号：US15728151

申请日：2017-10-09

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  Stephen P. King

IPC: G06F13/28 ,  G06F13/38 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/38 ,  G06F13/385 ,  G06F13/4004 ,  G06F13/4027

Abstract: Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a microcontroller, and the self-selecting bus decoder may determine a response of the peripheral device to requests from the microcontroller.

公开(公告)号：US20170371811A1

公开(公告)日：2017-12-28

申请号：US15534978

申请日：2015-12-29

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G06F13/12 ,  G06F13/16 ,  G06F13/28 ,  G06F13/42

CPC classification number: G06F9/4498 ,  G06F13/126 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/38 ,  G06F13/4282

Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.

公开(公告)号：US20170098157A1

公开(公告)日：2017-04-06

申请号：US15286229

申请日：2016-10-05

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  Michael C. Leventhal ,  Jeffery M. Tanner ,  Inderjit Singh Bains

IPC: G06N3/08

Abstract: An automaton is implemented in a state machine engine. The automaton is configured to observe data from a beginning of an input data stream until a point when an end of data (EOD) signal is seen. Additionally the automaton is configured to report an event only when one and only one occurrence of a target symbol is seen in the input data stream.

公开(公告)号：US20160239462A1

公开(公告)日：2016-08-18

申请号：US15137877

申请日：2016-04-25

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06F15/80 ,  G06N5/00

Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.

Abstract translation: 提供了用于模式识别处理器的多级分层路由矩阵。 一个这样的路由矩阵可以包括在矩阵的层内和之间的一个或多个可编程和/或不可编程的连接。 这些连接可以将路由线路耦合到特征单元，组，行，块或模式识别处理器的任何其他组件的布置。

公开(公告)号：US09275290B2

公开(公告)日：2016-03-01

申请号：US14223507

申请日：2014-03-24

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes ,  Irene Junjuan Xu ,  Paul Glendenning

IPC: G06F7/38 ,  G06K9/00 ,  G06F17/30 ,  H04L12/883 ,  G06F9/44

CPC classification number: G06F13/1673 ,  G06F9/4498 ,  G06F13/124 ,  G06F13/4022 ,  G06F13/4282 ,  G06F17/30516 ,  G06K9/00496 ,  G06K9/00973 ,  G06K9/00979 ,  H04L49/9021

Abstract: A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer also includes a second port configured to selectively provide the signal to a first routing line of a block of a state machine at a first time. The routing buffer further includes a third port configured to selectively provide the signal to a second routing line of the block of the state machine at the first time.

Abstract translation: 设备包括路由缓冲区。 路由缓冲器包括被配置为接收与数据流的至少一部分的分析有关的信号的第一端口。 路由缓冲器还包括被配置为在第一时间将信号选择性地提供给状态机的块的第一路由线的第二端口。 路由缓冲器还包括被配置为在第一时间将信号选择性地提供给状态机的块的第二路由选择线的第三端口。