公开(公告)号：US08659952B2

公开(公告)日：2014-02-25

申请号：US12169142

申请日：2008-07-08

申请人： Ming-Chang Kuo ,  Chao-I Wu

发明人： Ming-Chang Kuo ,  Chao-I Wu

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0475 ,  G11C16/12

摘要： A method of operating a non-volatile memory having a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer close to the drain region is a data storage region. Before prosecuting the operation, electrons have been injected into the auxiliary charge region. When prosecuting the programming operation, a first voltage is applied to the gate, a second voltage is applied to the source region, a third voltage is applied to the drain region and a fourth voltage is applied to the substrate. The first voltage is greater than the fourth voltage, the third voltage is greater than the second voltage, and the second voltage is greater than the fourth voltage to initiate a channel initiated secondary hot electron injection to inject electrons into the data storage region.

摘要翻译： 提供一种操作具有基板，栅极，电荷俘获层，源极区域和漏极区域的非易失性存储器的方法。 靠近源区的电荷捕获层是辅助电荷区，靠近漏极区的电荷捕获层是数据存储区。 在起诉前，电子注入到辅助电荷区域。 当起动编程操作时，向栅极施加第一电压，将第二电压施加到源极区域，向漏极区域施加第三电压，并向衬底施加第四电压。 第一电压大于第四电压，第三电压大于第二电压，第二电压大于第四电压，以启动通道启动的次级热电子注入以将电子注入数据存储区域。

公开(公告)号：US07242052B2

公开(公告)日：2007-07-10

申请号：US11180080

申请日：2005-07-11

申请人： Ming-Chang Kuo ,  Chao-I Wu

发明人： Ming-Chang Kuo ,  Chao-I Wu

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/7883 ,  H01L29/7885

摘要： A stacked structure is formed over a substrate, and the stacked structure has a gate dielectric layer and a floating gate thereon. A first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed over the top and the sidewalls of the stacked structure and the exposed substrate. A charge storage layer covers over the top and sidewalls of the stacked structure. Also, a pair of auxiliary gates is formed over the substrate beside the charge storage layer, and a gap is between the auxiliary gates and the charge storage layer.

摘要翻译： 堆叠结构形成在衬底上，堆叠结构在其上具有栅介电层和浮栅。 第一电介质层，第二电介质层和第三电介质层分别形成在层叠结构的顶部和侧壁以及暴露的基板上。 电荷存储层覆盖层叠结构的顶部和侧壁。 此外，在电荷存储层旁边的基板上形成一对辅助栅极，并且在辅助栅极和电荷存储层之间形成间隙。

公开(公告)号：US20060240618A1

公开(公告)日：2006-10-26

申请号：US11180080

申请日：2005-07-11

申请人： Ming-Chang Kuo ,  Chao-I Wu

发明人： Ming-Chang Kuo ,  Chao-I Wu

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/7883 ,  H01L29/7885

摘要： A method of fabricating a non-volatile memory is provided. A stacked structure is formed over a substrate, and the stacked structure has a gate dielectric layer and a floating gate thereon. A first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed over the top and the sidewalls of the stacked structure and the exposed substrate. A charge storage layer covers over the top and sidewalls of the stacked structure. Also, a pair of auxiliary gates is formed over the substrate beside the charge storage layer, and a gap is between the auxiliary gates and the charge storage layer.

摘要翻译： 提供了一种制造非易失性存储器的方法。 堆叠结构形成在衬底上，堆叠结构在其上具有栅介电层和浮栅。 第一电介质层，第二电介质层和第三电介质层分别形成在层叠结构的顶部和侧壁以及暴露的基板上。 电荷存储层覆盖层叠结构的顶部和侧壁。 此外，在电荷存储层旁边的基板上形成一对辅助栅极，并且在辅助栅极和电荷存储层之间形成间隙。

公开(公告)号：US20080316810A1

公开(公告)日：2008-12-25

申请号：US11767980

申请日：2007-06-25

申请人： Ming-Chang Kuo ,  Chao-I Wu

发明人： Ming-Chang Kuo ,  Chao-I Wu

IPC分类号： G11C11/00 ,  G11C16/04 ,  G11C7/10 ,  H01L29/788

CPC分类号： H01L29/42324 ,  G11C11/4125 ,  G11C14/00 ,  G11C14/0063

摘要： A memory unit is provided herein. Two non-volatile devices are used to store a logic state of the memory unit into the non-volatile devices. Although a power supply for the memory unit is shut down, the non-volatile devices still keep the data stored therein. The present invention not only has an advantage of high speed operation of a static random access memory (SRAM), but also has a function for storing data of a non-volatile memory.

摘要翻译： 本文提供了存储单元。 两个非易失性设备用于将存储器单元的逻辑状态存储到非易失性设备中。 虽然存储器单元的电源被关闭，但是非易失性设备仍然保持存储在其中的数据。 本发明不仅具有静态随机存取存储器（SRAM）的高速操作的优点，而且具有用于存储非易失性存储器的数据的功能。

公开(公告)号：US08467238B2

公开(公告)日：2013-06-18

申请号：US12946636

申请日：2010-11-15

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0033 ,  G11C13/0035

摘要： The control circuit performs a reset operation and a set operation that change the resistance states of phase change memory cells of the array. The control circuit changes at least one parameter, of at least one of the reset operation and the set operation for future operations. This change is responsive to an indicator of degraded memory state retention of the array.

摘要翻译： 控制电路进行改变阵列的相变存储单元的电阻状态的复位动作和设定动作。 控制电路至少改变一个参数，至少一个复位操作和设置操作中的一个参数用于将来的操作。 该更改响应于阵列的内存状态保留降级的指示符。

公开(公告)号：US08432745B2

公开(公告)日：2013-04-30

申请号：US13184189

申请日：2011-07-15

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C16/00

CPC分类号： H01L21/28282 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/11568 ,  H01L29/7923

摘要： A non-volatile VG memory array employing memory semiconductor cells capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in associating with at least one electrical insulating layer, such as an oxide, is disclosed. Bit lines of the memory array are capable of transmitting positive voltage to reach the source/drain regions of the memory cells of the array. A method that includes the hole injection erasure of the memory cells of the array that lowers the voltage threshold of the memory cells to a value lower than the initial voltage threshold of the cells is disclosed. The hole injection induced lower voltage threshold reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened. The programming and read steps reduce leakage current of the memory cells in the array.

摘要翻译： 公开了一种采用存储器半导体单元的非易失性VG存储器阵列，该存储器半导体单元能够存储与至少一个电绝缘层（例如氧化物）相结合的分层的非导电电荷俘获电介质（例如氮化硅）的两比特信息。 。 存储器阵列的位线能够传输正电压以到达阵列的存储器单元的源极/漏极区域。 公开了一种方法，其包括将阵列的存储单元的空穴注入擦除将存储单元的电压阈值降低到低于单元的初始电压阈值的值。 空穴注入诱导的较低电压阈值降低了第二位效应，使得位的编程和未编程电压阈值之间的操作窗口变宽。 编程和读取步骤减少阵列中存储单元的泄漏电流。

公开(公告)号：US08295094B2

公开(公告)日：2012-10-23

申请号：US13168536

申请日：2011-06-24

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C11/34

CPC分类号： H01L21/28282 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/107 ,  H01L29/78654 ,  H01L29/792

摘要： A method of operating a memory cell for 3D array of this invention is described as follows. Carriers of a first type are injected into a charge storage layer of the memory cell by applying a double-side biased (DSB) voltage to double sides of the memory cell. Carriers of a second type are injected into the charge storage layer by applying FN voltages.

摘要翻译： 本发明的3D阵列的存储单元的操作方法如下。 通过在存储单元的双面施加双面偏置（DSB）电压将第一类型的载体注入存储单元的电荷存储层。 通过施加FN电压将第二类型的载体注入电荷存储层。

公开(公告)号：US20120120723A1

公开(公告)日：2012-05-17

申请号：US12946636

申请日：2010-11-15

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C11/21

CPC分类号： G11C13/0004 ,  G11C13/0033 ,  G11C13/0035

摘要： The control circuit performs a reset operation and a set operation that change the resistance states of phase change memory cells of the array. The control circuit changes at least one parameter, of at least one of the reset operation and the set operation for future operations. This change is responsive to an indicator of degraded memory state retention of the array.

摘要翻译： 控制电路进行改变阵列的相变存储单元的电阻状态的复位动作和设定动作。 控制电路至少改变一个参数，至少一个复位操作和设置操作中的一个参数用于将来的操作。 该变化响应于阵列的内存状态保持降低的指示符。

公开(公告)号：US20110255349A1

公开(公告)日：2011-10-20

申请号：US13168536

申请日：2011-06-24

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C16/10

CPC分类号： H01L21/28282 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/107 ,  H01L29/78654 ,  H01L29/792

摘要： A method of operating a memory cell for 3D array of this invention is described as follows. Carriers of a first type are injected into a charge storage layer of the memory cell by applying a double-side biased (DSB) voltage to double sides of the memory cell. Carriers of a second type are injected into the charge storage layer by applying FN voltages.

摘要翻译： 本发明的3D阵列的存储单元的操作方法如下。 通过在存储单元的双面施加双面偏置（DSB）电压将第一类型的载体注入存储单元的电荷存储层。 通过施加FN电压将第二类型的载体注入电荷存储层。

公开(公告)号：US07986564B2

公开(公告)日：2011-07-26

申请号：US12233904

申请日：2008-09-19

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C16/04

CPC分类号： H01L21/28282 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/11568 ,  H01L29/7923

摘要： A non-volatile VG memory array employing memory semiconductor cells capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in associating with at least one electrical insulating layer, such as an oxide, is disclosed. Bit lines of the memory array are capable of transmitting positive voltage to reach the source/drain regions of the memory cells of the array. A method that includes the hole injection erasure of the memory cells of the array that lowers the voltage threshold of the memory cells to a value lower than the initial voltage threshold of the cells is disclosed. The hole injection induced lower voltage threshold reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened. The programming and read steps reduce leakage current of the memory cells in the array.

摘要翻译： 公开了一种采用存储器半导体单元的非易失性VG存储器阵列，该存储器半导体单元能够存储与至少一个电绝缘层（例如氧化物）相结合的分层的非导电电荷俘获电介质（例如氮化硅）的两比特信息。 。 存储器阵列的位线能够传输正电压以到达阵列的存储器单元的源极/漏极区域。 公开了一种方法，其包括将阵列的存储单元的空穴注入擦除将存储单元的电压阈值降低到低于单元的初始电压阈值的值。 空穴注入诱导的较低电压阈值降低了第二位效应，使得位的编程和未编程电压阈值之间的操作窗口变宽。 编程和读取步骤减少阵列中存储单元的泄漏电流。