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61.发明授权Method of forming a crack stop structure and diffusion barrier in integrated circuits 有权在集成电路中形成裂纹停止结构和扩散势垒的方法公开(公告)号：US06383893B1
公开(公告)日：2002-05-07
申请号：US09752622
申请日：2000-12-28
IPC分类号： H01L2146
CPC分类号： H01L23/585 , H01L2924/0002 , Y10S438/94 , H01L2924/00
摘要： A method for forming a crack stop structure and a barrier to the diffusion of oxygen and water vapor in integrated circuits is provided.
摘要翻译： 提供了一种形成裂纹停止结构的方法以及集成电路中氧气和水蒸气扩散的障碍。
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公开(公告)号：US06344125B1
公开(公告)日：2002-02-05
申请号：US09544053
申请日：2000-04-06
IPC分类号： C25D502
CPC分类号： C25D7/123 , H01L21/2885 , H01L21/32051
摘要： A process for the electrolytic deposition of a metal, preferably copper or an alloy of copper, directly onto a barrier layer coated on a dielectric layer. The process is advantageous because it electrolytically deposits metal in a pattern that is either the duplicate of a first conductive pattern under the dielectric or the inverse image of the first conductive pattern, depending on the first conductive pattern shape. Thus, metal is deposited on the barrier layer duplicating a first conductive pattern under the dielectric layer when the first pattern is a serpentine pattern and the metal deposits in the spaces between the conductive lines of a first conductive pattern of a discrete passive element such as a spiral.
摘要翻译： 一种用于将金属，优选铜或铜合金电解沉积到涂覆在电介质层上的阻挡层上的方法。 该方法是有利的，因为它取决于第一导电图案形状，电解沉积在第一导电图案的电介质下的第一导电图案的副本或第一导电图案的逆图像的图案中的金属。 因此，当第一图案是蛇形图案时，金属沉积在阻挡层上，复制第一导电图案下方的第一导电图案，并且金属沉积在离散无源元件的第一导电图案的导线之间的空间中，例如 螺旋。
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公开(公告)号：US06339024B1
公开(公告)日：2002-01-15
申请号：US09605728
申请日：2000-06-28
申请人： Kevin S. Petrarca , John E. Heidenreich, III , Judith M. Rubino , Carlos J. Sambucetti , Richard P. Volant , George F. Walker
发明人： Kevin S. Petrarca , John E. Heidenreich, III , Judith M. Rubino , Carlos J. Sambucetti , Richard P. Volant , George F. Walker
IPC分类号： H01L2044
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/13022 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/14
摘要： A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 &mgr;m. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.
摘要翻译： 一种制造集成电路的方法，其中提供具有大于或等于1.5μm厚度的集成电路的最上半导体层中的导电结构。 导电结构的厚度足够大，以有效地保护最高半导体层下面的任何层免受来自压力（例如由测试探针施加的压力）的损害。 在优选的实施方案中，传统的铝TD匀染被丢弃，有利于沉积在增厚的导电层上的金。
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公开(公告)号：US09511918B2
公开(公告)日：2016-12-06
申请号：US13340776
申请日：2011-12-30
CPC分类号： B65D79/02 , A61J1/03 , A61J2200/72 , B65D41/04 , B65D55/10 , B65D2213/00
摘要： Method and apparatus to provide a self-locking container to prevent unwanted access to materials stored in the container as a result of exposure to conditions that compromise the effectiveness or safety of the materials. A container may be threaded to receive a threaded lid, and the container may comprise a bolt movable within a channel from a retracted position, which allows the lid to be threadably connected or removed, to a locked position, which prevents removal of the lid. The bolt is movable to the locked position by a drive member, such as a bimetallic strip or a shape-memory element that drive the bolt in response to exposure to the condition that compromises the material.
摘要翻译： 提供自锁容器的方法和装置，以防止由于暴露于损害材料的有效性或安全性的条件而导致存储在容器中的材料的不期望的访问。 容器可以是螺纹以接收带螺纹的盖子，并且容器可以包括螺栓，该螺栓可在通道内从缩回位置移动，该缩回位置允许盖子被螺纹连接或移除到锁定位置，从而防止盖子移除。 螺栓通过驱动构件（例如双金属条或形状记忆元件）可移动到锁定位置，该双金属条或形状记忆元件响应于暴露于损害材料的状况而驱动螺栓。
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公开(公告)号：US08665575B2
公开(公告)日：2014-03-04
申请号：US13166842
申请日：2011-06-23
申请人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Krause , Zhengwen Li , Kevin S. Petrarca , Gerd Pfeiffer , Kevin Prettyman , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Krause , Zhengwen Li , Kevin S. Petrarca , Gerd Pfeiffer , Kevin Prettyman , Carl J. Radens , Brian C. Sapp
IPC分类号： H02H5/04
CPC分类号： H02H7/20 , H01L31/02021 , H02H5/047 , Y02E10/50
摘要： A photovoltaic module (10) with a plurality of solar cells (20) interconnected in serial and/or parallel arrangement within the module (10) is equipped with an overheat protection system (30) for suppressing damages of the photovoltaic module (10) due to defects of the solar cells (20). The overheat protection system (30) comprises a heat sensor (32) which is thermally coupled to a solar cell (20). The heat sensor (32) is physically integrated into an electrical switch (34, 36, 38) which is electrically connected to said solar cell (20).
摘要翻译： 具有在模块（10）内以串联和/或并联布置互连的多个太阳能电池（20）的光伏模块（10）装备有过热保护系统（30），用于抑制光伏模块（10）的损坏 涉及太阳能电池的缺陷（20）。 过热保护系统（30）包括热耦合到太阳能电池（20）的热传感器（32）。 热传感器（32）物理地集成在电连接到所述太阳能电池（20）的电开关（34,36,38）中。
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66.发明申请METHOD AND SYSTEM TO PREDICT LITHOGRAPHY FOCUS ERROR USING SIMULATED OR MEASURED TOPOGRAPHY 有权使用模拟或测量的地形来预测地震聚焦误差的方法和系统公开(公告)号：US20120194792A1
公开(公告)日：2012-08-02
申请号：US13014803
申请日：2011-01-27
申请人： Brian Christopher Sapp , Choongyeun Cho , Lawrence A. Clevenger , Laertis Economikos , Bernhard R. Liegl , Kevin S. Petrarca , Roger Allan Quon
发明人： Brian Christopher Sapp , Choongyeun Cho , Lawrence A. Clevenger , Laertis Economikos , Bernhard R. Liegl , Kevin S. Petrarca , Roger Allan Quon
IPC分类号： G03B27/52
CPC分类号： G03F7/7065 , G03F7/70066 , G03F7/705 , G03F7/70525 , G03F7/70641 , G03F9/7026 , G06F17/5009 , G06F17/5081
摘要： A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.
摘要翻译： 公开了使用芯片形貌数据来预测光刻聚焦误差的方法和系统。 可以测量或模拟地形数据的芯片地形数据。 平面最适合地形数据，并计算残差。 然后，残差用于对聚焦误差进行预测。 金属与电介质的密度比也可用作确定预测的聚焦误差的因素。
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公开(公告)号：US08159060B2
公开(公告)日：2012-04-17
申请号：US12608368
申请日：2009-10-29
IPC分类号： H01L23/02
CPC分类号： H01L23/5389 , H01L21/76898 , H01L24/80 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2924/12044
摘要： Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.
摘要翻译： 第一基板和第二基板中的每一个包括具有耐扩散电介质材料如氮化硅的表面。 凹陷区域形成在耐扩散电介质材料中，并且填充有可粘结介电材料。 第一和第二基板中的金属焊盘和可接合的介质材料部分的图案可以具有镜面对称性。 第一和第二基板通过金属焊盘和可接合的介电材料部分之间的触点之间的触点进行物理接触和接合。 通过基底通孔（TSV）结构通过键合介电材料部分形成。 位于TSV结构周围的每对键合的电介质材料部分之间的界面由两个扩散电阻的介电材料层封装，使得接合界面处的金属的扩散被包含在每对键合介电材料部分内。
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公开(公告)号：US20110124135A1
公开(公告)日：2011-05-26
申请号：US12947227
申请日：2010-11-16
IPC分类号： H01L21/66
CPC分类号： H01L31/1876 , H01L31/18 , H02S50/10 , Y02E10/50 , Y02P70/521
摘要： The invention relates to a method for assembly of solar cell modules by arranging a multitude pre-manufactured, individualized solar cells for forming a matrix of solar cells for the solar cell module; depositing a metallization layer at least partially on at least one surface of the matrix of solar cells for forming the solar cell module; testing electrical function at least of the solar cell module; depositing a passivation layer on a surface of the solar cell module. In another aspect the invention relates to a manufacturing system for a solar cell module and a solar cell module (26) comprising a matrix of pre-manufactured and individualized solar cells and manufactured according to the aforementioned method.
摘要翻译： 本发明涉及一种太阳能电池组件的组装方法，该方法通过布置用于形成用于太阳能电池模块的太阳能电池阵列的多个预制的个性化太阳能电池; 至少部分地在太阳能电池基体的至少一个表面上沉积金属化层以形成太阳能电池模块; 至少测试太阳能电池模块的电气功能; 在太阳能电池模块的表面上沉积钝化层。 另一方面，本发明涉及一种太阳能电池模块的制造系统和太阳能电池模块（26），其包括根据上述方法制造的预制和个性化太阳能电池的矩阵。
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69.发明授权Fuse link structures using film stress for programming and methods of manufacture 有权使用膜应力的熔断器连接结构进行编程和制造方法公开(公告)号：US07892926B2
公开(公告)日：2011-02-22
申请号：US12508962
申请日：2009-07-24
IPC分类号： H01L21/336
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, forming an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.
摘要翻译： 形成可编程熔丝结构的方法包括在衬底中形成至少一个浅沟槽隔离（STI），在至少一个STI上形成e-熔丝，并在该电熔丝上沉积层间电介质（ILD）层。 另外，该方法包括移除电子熔丝下的至少一个STI的至少一部分以在e熔丝的一部分下方提供空气间隙，并将e-fuse上的ILD层的至少一部分移除到 在电子熔断器的部分上方提供气隙。
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公开(公告)号：US07851919B2
公开(公告)日：2010-12-14
申请号：US12701045
申请日：2010-02-05
IPC分类号： H01L21/40
CPC分类号： H01L23/5329 , H01L21/76837 , H01L21/76885 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.
摘要翻译： 公开了包括金属互连的金属互连和IC芯片。 该方法的一个实施例可以包括提供直到并包括中间线（MOL）层的集成电路（IC）芯片，MOL层包括定位在第一电介质内的触点; 使第一电介质凹陷，使得接触延伸超过第一电介质的上表面; 在所述第一电介质上形成第二电介质，使得所述第二电介质围绕所述接触的至少一部分，所述第二电介质具有比所述第一电介质更低的介电常数; 在所述第二电介质上形成平坦化层; 通过平坦化层形成开口并进入到接触件的第二电介质中; 并在开口中形成金属以形成金属互连。
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