-
公开(公告)号：US06339024B1
公开(公告)日：2002-01-15
申请号：US09605728
申请日：2000-06-28
申请人： Kevin S. Petrarca , John E. Heidenreich, III , Judith M. Rubino , Carlos J. Sambucetti , Richard P. Volant , George F. Walker
发明人： Kevin S. Petrarca , John E. Heidenreich, III , Judith M. Rubino , Carlos J. Sambucetti , Richard P. Volant , George F. Walker
IPC分类号： H01L2044
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/13022 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/14
摘要： A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 &mgr;m. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.
摘要翻译： 一种制造集成电路的方法，其中提供具有大于或等于1.5μm厚度的集成电路的最上半导体层中的导电结构。 导电结构的厚度足够大，以有效地保护最高半导体层下面的任何层免受来自压力（例如由测试探针施加的压力）的损害。 在优选的实施方案中，传统的铝TD匀染被丢弃，有利于沉积在增厚的导电层上的金。
-
公开(公告)号：US07355271B2
公开(公告)日：2008-04-08
申请号：US10573561
申请日：2003-09-30
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L21/568 , H01L21/6835 , H01L23/5387 , H01L24/24 , H01L24/82 , H01L25/0652 , H01L25/50 , H01L2221/68359 , H01L2221/68372 , H01L2224/04042 , H01L2224/04105 , H01L2224/05554 , H01L2224/18 , H01L2224/24137 , H01L2224/48091 , H01L2224/48227 , H01L2224/49431 , H01L2224/49433 , H01L2224/73209 , H01L2224/73259 , H01L2224/73267 , H01L2224/82005 , H01L2224/9222 , H01L2225/06524 , H01L2225/06527 , H01L2225/06579 , H01L2225/06589 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/3511 , H01L2924/00014 , H01L2924/00
摘要： A three-dimensional package consisting of a plurality of folded integrated circuit chips (100, 110, 120) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip (130) is provided with additional interconnect wiring to a substrate (500), package or printed circuit board. Further described, is a method of providing a flexible arrangement of interconnected chips that are folded over into a three-dimensional arrangements to consume less aerial space when mounted on a substrate, second-level package or printed circuit board.
摘要翻译： 描述了由多个折叠集成电路芯片（100,110,120）组成的三维封装，其中至少一个芯片提供用于与堆叠的附加芯片的电连接的互连路径，并且至少一个芯片（130）是 提供与衬底（500），封装或印刷电路板的附加互连布线。 进一步描述的是提供互连芯片的柔性布置的方法，其被折叠成三维布置以在安装在基板，二级封装或印刷电路板上时消耗较少的空中空间。
-
公开(公告)号：US06924185B2
公开(公告)日：2005-08-02
申请号：US10680618
申请日：2003-10-07
申请人： David K. Anderson , Tien-Jen Cheng , Timothy J. Dalton , Christopher V. Jahnes , Andrew Lu , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant , George F. Walker
发明人： David K. Anderson , Tien-Jen Cheng , Timothy J. Dalton , Christopher V. Jahnes , Andrew Lu , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant , George F. Walker
IPC分类号： H01L23/525 , H01L21/336
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.
摘要翻译： 用于熔丝结构的方法和结构包括绝缘体层，穿过绝缘体层延伸到下面的布线层的多个熔丝电极，连接到电极的电镀熔丝元件和界面壁。 保险丝元件位于绝缘体的外部，并且在绝缘体和保险丝元件之间并置有间隙。 界面壁还包括第一侧壁，第二侧壁和内壁，其中内壁设置在间隙内。 熔丝电极彼此直径相对，并且熔丝元件垂直地设置在熔丝电极的上方。 保险丝元件是电镀，无电镀，或是超薄保险丝。
-
4.发明授权公开(公告)号：US07273806B2
公开(公告)日：2007-09-25
申请号：US10905013
申请日：2004-12-09
IPC分类号： H01L21/44
CPC分类号： H05K3/3468 , G01R1/07314 , G01R3/00 , H01L21/4853 , H01L21/6835 , H01L24/11 , H01L2224/13099 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01018 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/01058 , H01L2924/01066 , H01L2924/01067 , H01L2924/01068 , H01L2924/01075 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/19041 , H01L2924/19042 , H05K3/325 , H05K2201/09745 , H05K2201/10734 , H05K2203/0113 , H05K2203/0338 , H05K2203/128 , H05K2203/162 , H05K2203/167 , H01L2224/0401
摘要： Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on a conventional semiconductor substrate after the typical BEOL, and prior to packaging. The method may provide better electromigration characteristics, lower resistivity, and higher Q factors for conductive structures. In addition, the method is backwardly compatible and customizable.
摘要翻译： 公开了在封装之前在基板上形成导电结构的方法和根据该方法生成的测试探针结构。 导电结构包括通过注射成型的焊料形成的高纵横比结构。 本发明可以应用于在典型的BEOL之后以及在封装之前在常规半导体衬底上形成无源元件和互连。 该方法可以为导电结构提供更好的电迁移特性，较低的电阻率和更高的Q因子。 此外，该方法可以向后兼容并可定制。
-
公开(公告)号：US06534863B2
公开(公告)日：2003-03-18
申请号：US09781121
申请日：2001-02-09
申请人： George F. Walker , Ronald D. Goldblatt , Peter A. Gruber , Raymond R. Horton , Kevin S. Petrarca , Richard P. Volant , Tien-Jen Cheng
发明人： George F. Walker , Ronald D. Goldblatt , Peter A. Gruber , Raymond R. Horton , Kevin S. Petrarca , Richard P. Volant , Tien-Jen Cheng
IPC分类号： H01L2348
CPC分类号： H01L24/48 , H01L21/76865 , H01L21/76873 , H01L21/76879 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/85 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05083 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05169 , H01L2224/05181 , H01L2224/05556 , H01L2224/05572 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/11912 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/13116 , H01L2224/16 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85207 , H01L2924/0001 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00 , H01L2224/05552 , H01L2924/00015 , H01L2924/00012
摘要： A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.
-
公开(公告)号：US06927472B2
公开(公告)日：2005-08-09
申请号：US09992344
申请日：2001-11-14
申请人： David K. Anderson , Tien-Jen Cheng , Timothy J. Dalton , Christopher V. Jahnes , Andrew Lu , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant , George F. Walker
发明人： David K. Anderson , Tien-Jen Cheng , Timothy J. Dalton , Christopher V. Jahnes , Andrew Lu , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant , George F. Walker
IPC分类号： H01L23/525 , H01L21/336
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.
-
公开(公告)号：US08633580B2
公开(公告)日：2014-01-21
申请号：US13569231
申请日：2012-08-08
IPC分类号： H01L25/11
CPC分类号： H01L21/76879 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L24/16 , H01L24/29 , H01L24/82 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/29 , H01L2224/29298 , H01L2224/9202 , H01L2224/92144 , H01L2225/06541 , H01L2225/06575 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/12042 , H01L2924/14 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2224/05552 , H01L2924/00
摘要： A microelectronic assembly having a through hole extending through a first wafer (or chip) and a second wafer (or chip) are provided. The first and second wafers (or chips) have confronting faces and metallic features at the faces which are joined together to assemble the first and second wafers (or chips) leaving a gap between the confronting faces. A hole is etched in the first wafer (or chip), then material is sputtered to form a wall of material in the gap between wafers (or chips). Etching continues to extend the hole into or through the second wafer (or chip). The hole is filled to form a substantially vertical through silicon conductive via.
摘要翻译： 提供具有延伸穿过第一晶片（或芯片）和第二晶片（或芯片）的通孔的微电子组件。 第一和第二晶片（或芯片）在面处具有面对面和金属特征，所述表面和金属特征被连接在一起以组装在相对面之间留下间隙的第一和第二晶片（或芯片）。 在第一晶片（或芯片）中蚀刻孔，然后溅射材料以在晶片（或芯片）之间的间隙中形成材料壁。 蚀刻继续将孔扩展到第二晶片（或芯片）中或通过第二晶片（或芯片）。 该孔被填充以形成基本垂直的通过硅的导电通孔。
-
公开(公告)号：US20080132027A1
公开(公告)日：2008-06-05
申请号：US11954782
申请日：2007-12-12
申请人： Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , Kevin S. Petrarca , Anthony K. Stamper , Richard P. Volant
发明人： Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , Kevin S. Petrarca , Anthony K. Stamper , Richard P. Volant
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01L23/5228 , H01L23/53238 , H01L23/53295 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.
摘要翻译： 公开了避免半导体器件小型化的问题的电阻器及相关方法。 在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。 在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。 这两个实施方案可以单独使用或一起使用。 还公开了用于产生电阻器的相关方法。
-
公开(公告)号：US06995475B2
公开(公告)日：2006-02-07
申请号：US10666775
申请日：2003-09-18
申请人： Julie C. Biggs , Tien-Jen Cheng , David E. Eichstadt , Lisa A. Fanti , Jonathan H. Griffith , Randolph F. Knarr , Sarah H. Knickerbocker , Kevin S. Petrarca , Roger A. Quon , Wolfgang Sauter , Kamalesh K. Srivastava , Richard P. Volant
发明人： Julie C. Biggs , Tien-Jen Cheng , David E. Eichstadt , Lisa A. Fanti , Jonathan H. Griffith , Randolph F. Knarr , Sarah H. Knickerbocker , Kevin S. Petrarca , Roger A. Quon , Wolfgang Sauter , Kamalesh K. Srivastava , Richard P. Volant
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/04042 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05181 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/4847 , H01L2224/48624 , H01L2224/48644 , H01L2224/48655 , H01L2224/85205 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/04953 , H01L2924/05042 , H01L2924/12042 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.
摘要翻译： 一种在（I / C）芯片中形成引线键合的方法，包括：提供具有导电焊盘的I / C芯片，所述导电焊盘与覆盖所述焊盘的至少一层电介质材料进行引线接合; 通过暴露所述垫的一部分的电介质材料形成开口。 在衬垫的暴露表面和开口表面上形成至少第一导电层。 在第一导电层上形成种子层; 在种子层上施加光致抗蚀剂; 曝光和显影光致抗蚀剂，其显露出围绕开口的种子层的表面; 去除暴露的种子层; 去除开口中的光致抗蚀剂材料，露出种子层。 在开口中的种子层上电镀至少一层第二导电材料层，以及去除围绕开口的电介质层上的第一导电层。 本发明还包括所得到的结构。
-
公开(公告)号：US06762667B2
公开(公告)日：2004-07-13
申请号：US10465451
申请日：2003-06-19
申请人： Richard P. Volant , David Angell , Donald F. Canaperi , Joseph T. Kocis , Kevin S. Petrarca , Kenneth J. Stein , William C. Wille
发明人： Richard P. Volant , David Angell , Donald F. Canaperi , Joseph T. Kocis , Kevin S. Petrarca , Kenneth J. Stein , William C. Wille
IPC分类号： H01H3752
CPC分类号： B81B3/001 , B81B2201/014 , H01H59/0009 , H01H2059/0072
摘要： A method of fabricating and the structure of a micro-electromechanical switch (MEMS) device provided with self-aligned spacers or bumps is described. The spacers are designed to have an optimum size and to be positioned such that they act as a detent mechanism for the switch to minimize problems caused by stiction. The spacers are fabricated using standard semiconductor techniques typically used for the manufacture of CMOS devices. The present method of fabricating these spacers requires no added depositions, no extra lithography steps, and no additional etching.
摘要翻译： 描述了一种制造和具有自对准间隔物或凸块的微机电开关（MEMS）装置的结构的方法。 间隔件被设计成具有最佳尺寸并且被定位成使得它们用作开关的制动机构以最小化由静摩擦引起的问题。 使用通常用于制造CMOS器件的标准半导体技术制造间隔物。 制造这些间隔物的本方法不需要附加的沉积，不需要额外的光刻步骤，也不需要额外的蚀刻。
-
-
-
-
-
-
-
-
-
搜索结果
104 条记录 (耗时 0.032 秒)
