公开(公告)号：US10224813B2

公开(公告)日：2019-03-05

申请号：US15080461

申请日：2016-03-24

Applicant: NVIDIA Corporation

Inventor： Sudhir Shrikantha Kudva ,  William J. Dally ,  Thomas Hastings Greer, III ,  Carl Thomas Gray

IPC: H02M3/157 ,  H02M3/158 ,  H02M1/08 ,  H02M1/00

Abstract: A system and method are provided for controlling a modified buck converter circuit. A pull-up switching mechanism that is coupled to an upstream terminal of an inductor within a modified buck converter circuit is enabled. A load current at the output of the modified buck regulator circuit is measured. A capacitor current associated with a capacitor that is coupled to a downstream terminal of the inductor is continuously sensed and the pull-up switching mechanism is disabled when the capacitor current is greater than a sum of the load current and an enabling current value.

公开(公告)号：US09928104B2

公开(公告)日：2018-03-27

申请号：US13922189

申请日：2013-06-19

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  James David Balfour ,  Ignacio Llamas Ubieto

IPC: G06F5/00 ,  G06F9/46

CPC classification number: G06F9/466

Abstract: A system, method, and computer program product are provided for accessing a queue. The method includes receiving a first request to reserve a data record entry in a queue, updating a queue state block based on the first request, and returning a response to the request. A second request is received to commit the data record entry and the queue state block is updated based on the second request.

公开(公告)号：US20180046916A1

公开(公告)日：2018-02-15

申请号：US15458837

申请日：2017-03-14

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Angshuman Parashar ,  Joel Springer Emer ,  Stephen William Keckler ,  Larry Robert Dennison

IPC: G06N3/08 ,  G06F7/523 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06F7/523 ,  G06F7/5443 ,  G06F2207/4824 ,  G06N3/04 ,  G06N3/0454 ,  G06N3/082 ,  G06N3/084

Abstract: A method, computer program product, and system perform computations using a sparse convolutional neural network accelerator. Compressed-sparse data is received for input to a processing element, wherein the compressed-sparse data encodes non-zero elements and corresponding multi-dimensional positions. The non-zero elements are processed in parallel by the processing element to produce a plurality of result values. The corresponding multi-dimensional positions are processed in parallel by the processing element to produce destination addresses for each result value in the plurality of result values. Each result value is transmitted to a destination accumulator associated with the destination address for the result value.

公开(公告)号：US09594700B2

公开(公告)日：2017-03-14

申请号：US13865136

申请日：2013-04-17

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: G06F12/10 ,  G06F13/16

CPC classification number: G06F13/161

Abstract: A method and a system are provided for controlling memory accesses. Memory access requests including at least a first speculative memory access request and a first non-speculative memory access request are received and a memory access request is selected from the memory access requests. A memory access command is generated to process the selected memory access request.

Abstract translation: 提供了一种用于控制存储器访问的方法和系统。 接收包括至少第一推测存储器访问请求和第一非推测存储器访问请求的存储器访问请求，并且从存储器访问请求中选择存储器访问请求。 生成存储器访问命令以处理所选择的存储器访问请求。

公开(公告)号：US09459635B2

公开(公告)日：2016-10-04

申请号：US13763516

申请日：2013-02-08

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: G05F1/00 ,  G05F1/10 ,  H02M3/158 ,  H02M1/00

CPC classification number: G05F1/10 ,  H02M3/1582 ,  H02M3/1584 ,  H02M2001/008

Abstract: A system and method are provided for regulating a voltage at a load. A current source is configured to provide a current to a voltage control mechanism and the voltage control mechanism is configured to provide a portion of the current to the load. The current is generated based on the portion of the current that is provided to the load. A system includes the current source, an upstream controller, and the voltage control mechanism that is coupled to the load. The upstream controller is coupled to the current source and is configured to control a current that is generated by the current source based on a portion of the current that is provided to the load.

Abstract translation: 提供一种用于调节负载电压的系统和方法。 电流源被配置为向电压控制机构提供电流，并且电压控制机构被配置为向负载提供电流的一部分。 基于提供给负载的电流部分产生电流。 系统包括电流源，上游控制器和耦合到负载的电压控制机构。 上游控制器耦合到电流源，并被配置为基于提供给负载的电流的一部分来控制由电流源产生的电流。

公开(公告)号：US09395738B2

公开(公告)日：2016-07-19

申请号：US13752289

申请日：2013-01-28

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: H02M3/158 ,  G05F3/02 ,  H02M1/00

CPC classification number: G05F3/02 ,  H02M3/1582 ,  H02M3/1588 ,  H02M2001/0016 ,  H02M2001/0032 ,  H02M2003/1586 ,  Y02B70/1425 ,  Y02B70/1466 ,  Y02B70/16

Abstract: A system and method are provided for regulating a voltage level at a load. The method configures a current control mechanism to generate a current through a first inductor and a second inductor that are coupled in series and configures a voltage control mechanism to provide a portion of the current to regulate the voltage level. The second inductor isolates the load from a parasitic capacitance of the current control mechanism. An electric power conversion device for regulating the voltage level at the load comprises the current control mechanism that is coupled to an electric power source and configured to generate a current through the first inductor and the second inductor that are coupled in series and the voltage control mechanism that is coupled to the second inductor and configured to provide a portion of the current to regulate the voltage level.

Abstract translation: 提供了一种用于调节负载电压电平的系统和方法。 该方法配置电流控制机制以通过串联耦合的第一电感器和第二电感器产生电流，并配置电压控制机构以提供电流的一部分来调节电压电平。 第二个电感器将负载与电流控制机构的寄生电容隔离开来。 用于调节负载电压电平的电力转换装置包括电流控制机构，该电流控制机构耦合到电源并被配置为产生通过串联耦合的第一电感器和第二电感器的电流，以及电压控制机构 其耦合到第二电感器并且被配置为提供电流的一部分以调节电压电平。

公开(公告)号：US09323774B2

公开(公告)日：2016-04-26

申请号：US13887216

申请日：2013-05-03

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: G06F17/30

CPC classification number: G06F17/30153

Abstract: A system and method are provided for representing pointers. An encoding type for a pointer structure referenced by a first cell of a data structure is determined. A first field of the pointer structure is encoded to indicate the encoding type. Further, a second field of the pointer structure is encoded according to the encoding type to indicate a location in memory where a cell structure corresponding to a second cell of the data structure is stored.

Abstract translation: 提供了一种用于表示指针的系统和方法。 确定由数据结构的第一单元引用的指针结构的编码类型。 指针结构的第一个字段被编码以指示编码类型。 此外，根据编码类型对指针结构的第二字段进行编码，以指示存储与数据结构的第二单元相对应的单元结构的存储器中的位置。

公开(公告)号：US09224449B2

公开(公告)日：2015-12-29

申请号：US13794563

申请日：2013-03-11

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: G11C11/406 ,  G11C29/02 ,  G11C29/50

CPC classification number: G11C11/406 ,  G11C11/40622 ,  G11C11/40626 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50016

Abstract: A system and method are provided for refreshing a dynamic memory. A first region of a memory is refreshed at a first refresh rate and a second region of the memory is refreshed at a second refresh rate that is different than the first refresh rate. A memory controller is configured to refresh the first region of a memory at the first refresh rate and refresh the second region of the memory at the second refresh rate.

Abstract translation: 提供了一种用于刷新动态存储器的系统和方法。 以第一刷新率刷新存储器的第一区域，并且以与第一刷新率不同的第二刷新率来刷新存储器的第二区域。 存储器控制器被配置为以第一刷新率刷新存储器的第一区域并以第二刷新率刷新存储器的第二区域。

公开(公告)号：US09171607B2

公开(公告)日：2015-10-27

申请号：US13938161

申请日：2013-07-09

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  John W. Poulton ,  Thomas Hastings Greer, III ,  Brucek Kurdo Khailany ,  Carl Thomas Gray

IPC: G11C11/40 ,  G11C11/4096 ,  G11C7/10 ,  H04L25/02

CPC classification number: G11C11/4096 ,  G11C7/1057 ,  G11C7/1069 ,  H04L25/0276

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a system function chip, and an MCM package configured to include the first processor chip and the system function chip. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The system function chip is configured to include a second GRS interface circuit. A first set of electrical traces are fabricated within the MCM package and coupled to the first GRS interface circuit and to the second GRS interface circuit. The first GRS interface circuit and second GRS interface circuit together provide a communication channel between the first processor chip and the system function chip.

Abstract translation: 包括多芯片模块（MCM）的互连芯片的系统包括第一处理器芯片，系统功能芯片和被配置为包括第一处理器芯片和系统功能芯片的MCM封装。 第一处理器芯片被配置为包括第一接地参考单端信令（GRS）接口电路。 系统功能芯片被配置为包括第二GRS接口电路。 在MCM封装内制造第一组电迹线，并耦合到第一GRS接口电路和第二GRS接口电路。 第一GRS接口电路和第二GRS接口电路一起提供第一处理器芯片和系统功能芯片之间的通信通道。

公开(公告)号：US09106235B2

公开(公告)日：2015-08-11

申请号：US13942614

申请日：2013-07-15

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: H04L7/00 ,  H03L7/00

CPC classification number: H03L7/00 ,  H04L7/0012 ,  H04L7/0037 ,  H04L7/0041

Abstract: A method and a system are provided for synchronizing a signal. A keep out window is defined relative to a second clock signal and an edge detection signal is generated that indicates if an edge of a first clock signal is within the keep out window. The edge detection signal may be filtered. An input signal is received in a domain corresponding to the first clock signal and a delayed input signal is generated. Based on the edge detection signal or the filtered edge detection signal, either the input signal or the delayed input signal is selected, to produce an output signal in a domain corresponding to the second clock signal.

Abstract translation: 提供了一种用于使信号同步的方法和系统。 相对于第二时钟信号定义保持窗口，并且生成指示第一时钟信号的边缘在保持输出窗口内的边缘检测信号。 可以对边缘检测信号进行滤波。 在对应于第一时钟信号的域中接收输入信号，并且产生延迟的输入信号。 基于边缘检测信号或滤波边沿检测信号，选择输入信号或延迟输入信号，以产生与第二时钟信号对应的域中的输出信号。