公开(公告)号：US08102712B2

公开(公告)日：2012-01-24

申请号：US12644408

申请日：2009-12-22

申请人： Akira Goda ,  Andrew Bickler ,  Haitao Liu ,  Tomoharu Tanaka

发明人： Akira Goda ,  Andrew Bickler ,  Haitao Liu ,  Tomoharu Tanaka

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C16/0408 ,  G11C16/06

摘要： A NAND memory array is programmed applying a programming voltage Vpgm as a double pulse programming pulse if a data pattern associated with memory cells that are to be programmed form a two-sided column-stripe (CS2) data pattern. The CS2 data pattern comprises a memory cell that is not to be programmed directly between two memory cells that are to be programmed, such that a channel associated with the memory cell that is not to be programmed has an applied boost voltage, and the channels associated with the two memory cells that are to be programmed have an applied programming voltage. The first memory cell of the two memory cells is programmed by the first programming voltage pulse and the second memory cell is programmed by the second programming voltage pulse. A programming voltage Vpgm is applied as a single pulse if a CS2 data pattern is not formed.

摘要翻译： 如果与要编程的存储器单元相关联的数据模式形成双面列条带（CS2）数据模式，则NAND存储器阵列被编程为将编程电压Vpgm应用为双脉冲编程脉冲。 CS2数据模式包括不被直接编程在待编程的两个存储器单元之间的存储器单元，使得与不被编程的存储器单元相关联的通道具有施加的升压电压，并且所述通道相关联 要编程的两个存储单元具有应用的编程电压。 两个存储单元的第一存储单元由第一编程电压脉冲编程，第二存储单元由第二编程电压脉冲编程。 如果没有形成CS2数据模式，则将编程电压Vpgm作为单个脉冲施加。

公开(公告)号：US20100128529A1

公开(公告)日：2010-05-27

申请号：US12696279

申请日：2010-01-29

申请人： Akira Goda ,  Taehoon Kim ,  Doyle Rivers ,  Roger Porter

发明人： Akira Goda ,  Taehoon Kim ,  Doyle Rivers ,  Roger Porter

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C5/145 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621

摘要： Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.

摘要翻译： 具有用于根据正在编程的多电平单元的电平改变Vstep增量的切换点的方法和存储器包括在窄阈值电压情况下以较小的Vstep增量进行编程，并且在需要更快编程的较大Vstep增量下进行编程。

公开(公告)号：US20100052032A1

公开(公告)日：2010-03-04

申请号：US12588203

申请日：2009-10-07

申请人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

发明人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L21/76838 ,  H01L27/115 ,  H01L27/11521

摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.

摘要翻译： 非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

公开(公告)号：US07622762B2

公开(公告)日：2009-11-24

申请号：US12000396

申请日：2007-12-12

申请人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

发明人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L21/76838 ,  H01L27/115 ,  H01L27/11521

摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.

摘要翻译： 非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

公开(公告)号：US07606075B2

公开(公告)日：2009-10-20

申请号：US11407227

申请日：2006-04-19

申请人： Seiichi Aritome ,  Akira Goda

发明人： Seiichi Aritome ,  Akira Goda

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C16/0483

摘要： Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to source lines associated with a selected block of an array of memory cells and a second, different, potential is supplied to other source lines not associated with that block. By supplying a different potential to source lines of unselected blocks, current leakage can be mitigated.

摘要翻译： 利用NAND架构的非易失性存储器件适于执行读取操作，其中将第一电位提供给与存储器单元阵列的所选块相关联的源极线，并且将第二不同的电位提供给不相关的其它源极线 与那个块。 通过向未选择的块的源极线提供不同的电位，可以减轻电流泄漏。

公开(公告)号：US20080293201A1

公开(公告)日：2008-11-27

申请号：US12181978

申请日：2008-07-29

申请人： Akira Goda ,  Hiroyuki Nitta

发明人： Akira Goda ,  Hiroyuki Nitta

IPC分类号： H01L21/336

CPC分类号： H01L29/7881 ,  G11C16/0416 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526

摘要： A nonvolatile semiconductor memory includes: a device region and a device isolating region, which have a pattern with a striped form that extends in a first direction, and are alternately and sequentially disposed at a first pitch in a second direction that is perpendicular to the first direction; and a contact made of a first conductive material, which is connected to the device region and disposed at the first pitch in the second direction. On a cross section of the second direction, the bottom width of the contact is longer than the top width of the contact, and the bottom width is longer than the width of the device region.

摘要翻译： 非易失性半导体存储器包括：器件区域和器件隔离区域，其具有沿第一方向延伸的条纹形式的图案，并且在垂直于第一方向的第二方向上以第一间距交替地并且顺序地设置 方向; 以及由第一导电材料制成的接触件，其连接到器件区域并沿第二方向以第一间距设置。 在第二方向的横截面上，触点的底部宽度比触点的顶部宽度长，并且底部宽度比器件区域的宽度长。

公开(公告)号：US20080286919A1

公开(公告)日：2008-11-20

申请号：US11749980

申请日：2007-05-17

申请人： Akira Goda

发明人： Akira Goda

IPC分类号： H01L21/8238 ,  H01L21/3205

CPC分类号： H01L21/76229 ,  H01L21/82385 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS transistor comprising gate oxide and having a wide active area and/or a long channel, and the second transistor type may comprise a NAND comprising tunnel oxide and having a narrow active area and/or short gate length. The transistors are exposed to a nitridation ambient which, due to their differences in sizing, results in nitridizing the tunnel oxide in its entirely but only partially nitridizing the gate oxide. Various process embodiments and completed structures are disclosed.

摘要翻译： 在半导体器件制造期间使用的方法包括形成至少两种类型的晶体管。 第一晶体管类型可以包括包含栅极氧化物并具有宽有源面积和/或长沟道的CMOS晶体管，并且第二晶体管类型可以包括具有隧道氧化物的NAND并且具有窄的有源面积和/或短栅极长度。 晶体管暴露于氮化环境，由于它们的尺寸差异，导致隧道氧化物在其完全但仅部分氮化栅极氧化物中进行氮化。 公开了各种处理实施例和完成的结构。

公开(公告)号：US20070247908A1

公开(公告)日：2007-10-25

申请号：US11407227

申请日：2006-04-19

申请人： Seiichi Aritome ,  Akira Goda

发明人： Seiichi Aritome ,  Akira Goda

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/0483

摘要： Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to source lines associated with a selected block of an array of memory cells and a second, different, potential is supplied to other source lines not associated with that block. By supplying a different potential to source lines of unselected blocks, current leakage can be mitigated.

摘要翻译： 利用NAND架构的非易失性存储器件适于执行读取操作，其中将第一电位提供给与存储器单元阵列的所选块相关联的源极线，并且将第二不同的电位提供给不相关的其它源极线 与那个块。 通过向未选择的块的源极线提供不同的电位，可以减轻电流泄漏。

公开(公告)号：US07099190B2

公开(公告)日：2006-08-29

申请号：US10822177

申请日：2004-04-12

申请人： Mitsuhiro Noguchi ,  Akira Goda

发明人： Mitsuhiro Noguchi ,  Akira Goda

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G06F11/1008 ,  G11C16/0483

摘要： A data storage system, which includes a plurality of pages, each of which includes a plurality of first memory cells, from which at least binary data can be read-out a plurality of times without destruction; a circuit which receives data-output of at least one first page, detects an error in at least one bit of data, and outputs information of the error position; another circuit which determines whether data of an error bit is “1” or “0”. When the determination is “1” or “0”, the first memory cell of the first page is erased, and error-corrected data is written.

摘要翻译： 一种数据存储系统，其包括多个页面，每个页面包括多个第一存储器单元，至少二进制数据可从多个第一存储单元读出多次而不被破坏; 接收至少一个第一页的数据输出的电路检测至少一位数据中的错误，并输出错误位置的信息; 确定错误位的数据是“1”还是“0”的另一个电路。 当确定为“1”或“0”时，第一页的第一存储单元被擦除，并且写入纠错数据。

公开(公告)号：US07026241B2

公开(公告)日：2006-04-11

申请号：US10943250

申请日：2004-09-17

申请人： Akira Goda ,  Mitsuhiro Noguchi ,  Yuji Takeuchi ,  Hiroaki Hazama

发明人： Akira Goda ,  Mitsuhiro Noguchi ,  Yuji Takeuchi ,  Hiroaki Hazama

IPC分类号： H01L21/4763

CPC分类号： H01L27/11568 ,  H01L21/76838 ,  H01L23/485 ,  H01L23/522 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising element regions formed in a semiconductor substrate, conductor plugs embedded in an interlayer insulation film, and wiring layers connected to the plugs, wherein the plugs are arranged on a straight line orthogonal to a longitudinal direction of the wiring layer in the same pitch as the wiring layers such that the straight line and upper surfaces of the plugs are superposed each other, and when the plugs are viewed in a cross section parallel to a main surface of the substrate and a distance which is between those two edge points of each of the plugs where a split line which passes through a center of each of the plugs passes is defined as a contact diameter, the contact diameter has three or more maximum values and three or more minimum values while the split line is rotated in the cross section by 360 degrees.