公开(公告)号：US11256637B2

公开(公告)日：2022-02-22

申请号：US16829163

申请日：2020-03-25

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/20 ,  G06F13/42 ,  H04B1/38

Abstract: Systems, methods, and apparatus increase the number of slave devices that can be connected to a serial bus. The bus protocol may be an RFFE protocol, an SPMI protocol, an I3C protocol or another protocol usable on a serial bus. In various aspects of the disclosure, a method performed at a device coupled to a serial bus includes receiving a first datagram at a slave device coupled to a serial bus, where the first datagram includes a 4-bit broadcast address indicative of a broadcast datagram, a first command directed to an invalid register address, and a payload, determining an encapsulation protocol associated with the invalid register address, and responding to a second command carried in the payload when an 8-bit slave address in the payload matches an 8-bit slave identifier allocated to the slave device.

公开(公告)号：US20210242903A1

公开(公告)日：2021-08-05

申请号：US16780509

申请日：2020-02-03

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Soon-Seng Lau

IPC: H04B3/487 ,  H04L27/00 ,  H04B3/06

Abstract: Crosstalk amelioration systems and methods in a radio frequency front end (RFFE) communication system provide a host or master of an RFFE bus to monitor a weakly-driven data line in the RFFE bus while a clock line is actively providing a clock signal for trigger events at one or more slaves on the RFFE bus. If the host detects noise on the data line that looks like a sequence start condition (SSC) signal, the host further signals on the data line to negate the impact of the false SSC signal and thus avoid misinterpretation by the slaves.

公开(公告)号：US11023408B2

公开(公告)日：2021-06-01

申请号：US16405637

申请日：2019-05-07

Applicant: QUALCOMM Incorporated

Inventor： Radu Pitigoi-Aron ,  Chandan Pramod Attarde ,  Richard Dominic Wietfeldt ,  Lalan Jee Mishra

IPC: G06F13/42

Abstract: Systems, methods, and apparatus for communication over a serial bus in accordance with an I3C protocol are described that enable a slave device to request that a bus master device terminate a write transaction with the slave device. The serial bus may be operated according to an I3C single data rate protocol. In various aspects of the disclosure, a method performed at a master device coupled to a serial bus includes initiating a write transaction between the master device and a slave device, where the write transaction includes a plurality of data frames, and at least one data frame is configured with a transition bit in place of a parity bit. The method may include terminating the write transaction when the slave device drives a data line of the serial bus while receiving the transition bit.

公开(公告)号：US10733121B2

公开(公告)日：2020-08-04

申请号：US16392264

申请日：2019-04-23

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt ,  Sharon Graif ,  Lior Amarilio ,  Kishalay Haldar ,  Oren Nishry

IPC: G06F9/455 ,  G06F13/20 ,  G06F13/42

Abstract: Systems, methods, and apparatus for communicating virtual GPIO information generated at multiple source devices and directed to multiple destination devices. A method performed at a device coupled to a serial bus includes generating first virtual GPIO state information representative of state of one or more physical GPIO output pins, asserting a request to transmit the first virtual GPIO state information by driving a data line of the serial bus from a first state to a second state after a start code has been transmitted on a serial bus and before a first clock pulse is transmitted on a clock line of the serial bus, transmitting the first virtual GPIO state information as a first set of bits in a data frame associated with the start code, and receiving second virtual GPIO state information in a second set of bits in the data frame.

公开(公告)号：US10572410B2

公开(公告)日：2020-02-25

申请号：US16193853

申请日：2018-11-16

Applicant: QUALCOMM Incorporated

Inventor： Helena Deirdre O'Shea ,  Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Mohit Kishore Prasad ,  Amit Gil ,  Gary Chang

IPC: G06F13/42 ,  G06F13/20

Abstract: Systems, methods, and apparatus are described that provide for communicating coexistence messages over a multi-drop serial bus. A data communication method includes configuring a common memory map at each of a plurality of devices coupled to a serial bus, receiving at a first device coupled to the serial bus, first coexistence information directed to a second device coupled to the serial bus, generating at the first device, a coexistence message that includes the first coexistence information, and transmitting the coexistence message to the second device over the serial bus. The first coexistence information in the coexistence message may be addressed to a location in the common memory map calculated based on a destination address associated with the first coexistence information and a unique identifier of the first device.

公开(公告)号：US10474622B1

公开(公告)日：2019-11-12

申请号：US16036273

申请日：2018-07-16

Applicant: QUALCOMM Incorporated

Inventor： Richard Dominic Wietfeldt ,  Lalan Jee Mishra

IPC: G06F13/42 ,  G06F13/40

Abstract: Systems, methods, and apparatus for improving bus latency are described. A method performed at a transmitting device includes receiving a datagram to be transmitted from the transmitting device to a receiving device, determining whether a first serial bus coupling the transmitting device to the receiving device is available to transmit the datagram, determining whether a second serial bus coupling the transmitting device to the receiving device is available to transmit the datagram, transmitting the datagram over the first serial bus when the first serial bus is available, and transmitting the datagram over the second serial bus when the second serial bus is available and when the first serial bus is unavailable. The datagram is associated with a latency budget. The first or second serial bus may be available to transmit the datagram when active and likely to transmit the datagram within a time limit defined by the latency budget.

公开(公告)号：US20180267916A1

公开(公告)日：2018-09-20

申请号：US15989067

申请日：2018-05-24

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/362 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F13/4068 ,  G06F13/4282 ,  G06F13/4291

Abstract: A modified serial peripheral interface (SPI) is provided in each of a master device and a plurality of slave devices that does not use a slave select line. The master device may thus engage in full-duplex serial communication with each slave device through an SPI MOSI line, an SPI MISO line, and an SPI clock line.

公开(公告)号：US20180173665A1

公开(公告)日：2018-06-21

申请号：US15382102

申请日：2016-12-16

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F13/364 ,  G06F13/404

Abstract: Systems, methods, and apparatus are described that enable communication of in-band reset signals over a serial bus. A method performed at a slave device coupled to the serial bus includes configuring a reset controller to operate in one of plural modes, identifying a first reset pattern in signaling received from a multi-wire serial bus, complying with one or more transmissions defined by the protocol, asserting a reset input of a processing circuit in the slave device responsive to an identification of the first reset pattern when the reset controller is operated in a first mode, and ignoring the first reset pattern when the reset controller is operated in a second mode. The signaling received from the multi-wire serial bus may include one or more transmissions defined by a protocol used on the multi-wire serial bus. The reset controller may operate autonomously from the processing circuit in the first mode.

公开(公告)号：US09820158B2

公开(公告)日：2017-11-14

申请号：US13762125

申请日：2013-02-07

Applicant: QUALCOMM Incorporated

Inventor： George Chrisikos ,  Richard Dominic Wietfeldt

IPC: H04W16/14 ,  H04W72/12 ,  H04W88/04 ,  H04W88/06

CPC classification number: H04W16/14 ,  H04W72/1215 ,  H04W72/1231 ,  H04W88/04 ,  H04W88/06

Abstract: A user equipment (UE) may mitigate interference on the user equipment with two or more radios. In some instances, the UE may determine when communications of the two or more radios experience interference, in which two radios of the two or more radios operate with the same radio access technology. Further, the UE may alter an operating frequency of a first radio of the two radios to mitigate the interference.

公开(公告)号：US09747244B2

公开(公告)日：2017-08-29

申请号：US14540366

申请日：2014-11-13

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Mohit Kishore Prasad

IPC: G06F13/12 ,  G06F13/42 ,  G06F9/455

CPC classification number: G06F13/4221 ,  G06F9/45533 ,  G06F13/4273

Abstract: A virtual GPIO architecture for an integrated circuit is provided that both serializesvirtual GPIO signals and deserializes virtual GPIO signals without the need for an external clock.