公开(公告)号：US07767514B2

公开(公告)日：2010-08-03

申请号：US11406863

申请日：2006-04-18

申请人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

发明人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823412 ,  H01L27/0811 ,  H01L27/088 ,  H01L29/66537 ,  H01L29/7833

摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

摘要翻译： 本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。 本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为 在介电材料的下方并与导电掺杂的扩散区相邻。 形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。 当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

公开(公告)号：US07674670B2

公开(公告)日：2010-03-09

申请号：US11406893

申请日：2006-04-18

申请人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

发明人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823412 ,  H01L27/0811 ,  H01L27/088 ,  H01L29/66537 ,  H01L29/7833

摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

摘要翻译： 本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。 本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为 在介电材料的下方并与导电掺杂的扩散区相邻。 形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。 当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

公开(公告)号：US07394142B2

公开(公告)日：2008-07-01

申请号：US11204462

申请日：2005-08-16

申请人： Kurt D. Beigel

发明人： Kurt D. Beigel

IPC分类号： H01L29/00

CPC分类号： H01L27/0814 ,  H01L27/0629 ,  H01L29/417 ,  H01L29/861

摘要： A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of MOSFET diode-connected transistors. In addition, a method for manufacturing the bulk isolated PN diodes is recited.

摘要翻译： 制造大容量隔离PN二极管的技术。 具体地，提供了一种用一对体隔离PN二极管制造电压钳的技术。 另一个实施例提供了具有一对体耦合的PN二极管与一对MOSFET二极管连接的晶体管并联的电压钳位。 此外，还列举了用于制造体分离PN二极管的方法。

公开(公告)号：US07348652B2

公开(公告)日：2008-03-25

申请号：US10383893

申请日：2003-03-07

申请人： Kurt D. Beigel

发明人： Kurt D. Beigel

IPC分类号： H01L29/00 ,  G11C7/10

CPC分类号： H01L27/0814 ,  H01L27/0629 ,  H01L29/417 ,  H01L29/861

摘要： A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of MOSFET diode-connected transistors. In addition, a method for manufacturing the bulk isolated PN diodes is recited.

公开(公告)号：US06983404B2

公开(公告)日：2006-01-03

申请号：US09777036

申请日：2001-02-05

申请人： Douglas J. Cutter ,  Adrian E. Ong ,  Fan Ho ,  Kurt D. Beigel ,  Brett M. Debenham ,  Dien Luong ,  Kim Pierce ,  Patrick J. Mullarkey

发明人： Douglas J. Cutter ,  Adrian E. Ong ,  Fan Ho ,  Kurt D. Beigel ,  Brett M. Debenham ,  Dien Luong ,  Kim Pierce ,  Patrick J. Mullarkey

IPC分类号： G11C29/00

CPC分类号： G11C17/18

摘要： Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binary value indicates whether the resistance of the antifuse element is higher or lower than the known value of resistance. The method and apparatus are useful in verifying the programming of antifuse elements.

摘要翻译： 公开了用于检查集成电路中的反熔丝元件的电阻的方法和装置。 将基于反熔丝元件的电阻的电压与基于已知电阻的电压进行比较，并且生成其二进制值表示反熔丝元件的电阻是否高于或低于已知电阻值的输出信号。 该方法和装置在验证反熔丝元件的编程方面是有用的。

公开(公告)号：US06690611B2

公开(公告)日：2004-02-10

申请号：US10224989

申请日：2002-08-20

申请人： Douglas J. Cutter ,  Fan Ho ,  Kurt D. Beigel

发明人： Douglas J. Cutter ,  Fan Ho ,  Kurt D. Beigel

IPC分类号： G11C700

CPC分类号： G11C29/838

摘要： The cancellation of a redundant element of an integrated circuit with a cancel bank is disclosed. In one embodiment, a fuse or antifuse bank is coupled to the redundant element and permanently programmed to respond to the address of a defective primary element. If the redundant element is found to be defective, the fuse or antifuse bank is canceled, and a result the redundant element is also canceled. A cancel line of the fuse or antifuse bank, along with the cancel line of each of a plurality of other fuse or antifuse banks, is coupled to a cancel bank. The cancel bank comprises a multiplexer and a plurality of cancel antifuses less in number than the number of fuse or antifuse banks. The cancel antifuses are selectively enabled such that the fuse or antifuse bank coupled to the defective redundant element may be canceled.

摘要翻译： 公开了一种具有取消组的集成电路的冗余元件的取消。 在一个实施例中，熔丝或反熔丝组耦合到冗余元件并且被永久编程以响应有缺陷的主要元件的地址。 如果发现冗余元件有故障，则保险丝或反熔丝组被取消，结果冗余元件也被取消。 保险丝或反熔丝库的取消线连同多个其它熔丝或反熔丝组中的每一个的取消线耦合到取消库。 取消存储体包括一个多路复用器和多个抵抗熔丝或反熔丝的数量的抵消反熔丝。 选择性地启用取消反熔丝，使得耦合到有缺陷的冗余元件的熔丝或反熔丝组可被取消。

公开(公告)号：US06600687B2

公开(公告)日：2003-07-29

申请号：US10253844

申请日：2002-09-23

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

公开(公告)号：US06353564B1

公开(公告)日：2002-03-05

申请号：US09735157

申请日：2000-12-11

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C2900

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

公开(公告)号：US06351424B1

公开(公告)日：2002-02-26

申请号：US09634069

申请日：2000-08-08

申请人： Douglas J. Cutter ,  Fan Ho ,  Kurt D. Beigel

发明人： Douglas J. Cutter ,  Fan Ho ,  Kurt D. Beigel

IPC分类号： G11C700

CPC分类号： G11C29/838

摘要： The cancellation of a redundant element of an integrated circuit with a cancel bank is disclosed. In one embodiment, a fuse or antifuse bank is coupled to the redundant element and permanently programmed to respond to the address of a defective primary element. If the redundant element is found to be defective, the fuse or antifuse bank is canceled, and a result the redundant element is also canceled. A cancel line of the fuse or antifuse bank, along with the cancel line of each of a plurality of other fuse or antifuse banks, is coupled to a cancel bank. The cancel bank comprises a multiplexer and a plurality of cancel antifuses less in number than the number of fuse or antifuse banks. The cancel antifuses are selectively enabled such that the fuse or antifuse bank coupled to the defective redundant element may be canceled.

摘要翻译： 公开了一种具有取消组的集成电路的冗余元件的取消。 在一个实施例中，熔丝或反熔丝组耦合到冗余元件并且被永久编程以响应有缺陷的主要元件的地址。 如果发现冗余元件有故障，则保险丝或反熔丝组被取消，结果冗余元件也被取消。 保险丝或反熔丝库的取消线连同多个其它熔丝或反熔丝组中的每一个的取消线耦合到取消库。 取消存储体包括一个多路复用器和多个抵抗熔丝或反熔丝的数量的抵消反熔丝。 选择性地启用取消反熔丝，使得耦合到有缺陷的冗余元件的熔丝或反熔丝组可被取消。

公开(公告)号：US06335888B2

公开(公告)日：2002-01-01

申请号：US09735120

申请日：2000-12-11

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。