Data storage medium having a test mode
    61.
    发明申请
    Data storage medium having a test mode 有权
    具有测试模式的数据存储介质

    公开(公告)号:US20060006243A1

    公开(公告)日:2006-01-12

    申请号:US11176941

    申请日:2005-07-06

    IPC分类号: G06K19/06

    摘要: A data storage medium having a memory unit, a control unit, and an interface having contact pads for at least one voltage supply and one data transmission. Provision is made of a test signal generating device for generating test signals used to test the data storage medium. The data storage medium can be switched into a test mode in which the test signals are used for the test.

    摘要翻译: 一种具有存储单元,控制单元和具有用于至少一个电压源和一个数据传输的接触焊盘的接口的数据存储介质。 提供测试信号产生装置,用于产生用于测试数据存储介质的测试信号。 数据存储介质可以被切换成测试模式,其中测试信号用于测试。

    Parallel data bus
    62.
    发明申请
    Parallel data bus 审中-公开
    并行数据总线

    公开(公告)号:US20050289409A1

    公开(公告)日:2005-12-29

    申请号:US11165823

    申请日:2005-06-23

    IPC分类号: G01R31/28 G06F21/85 G11C29/00

    CPC分类号: G06F21/85

    摘要: A parallel data bus having a plurality of bus lines, and a bus mode switching device for switching between data transmission at a high data transmission rate and data transmission at high data integrity.

    摘要翻译: 具有多个总线的并行数据总线,以及用于在高数据传输速率的数据传输和高数据完整性的数据传输之间切换的总线模式切换装置。

    Calculating unit and method for performing an arithmetic operation with encrypted operands
    63.
    发明申请
    Calculating unit and method for performing an arithmetic operation with encrypted operands 有权
    用加密操作数执行算术运算的计算单元和方法

    公开(公告)号:US20050036618A1

    公开(公告)日:2005-02-17

    申请号:US10893163

    申请日:2004-07-16

    摘要: A calculating unit for performing an arithmetic operation with at least two operands, the at least two operands being encrypted, includes an arithmetic-logic unit with a first input for the first encrypted operand, a second input for the second encrypted operand, a third input for an encryption parameter and an output for an encrypted result of the operation, the arithmetic-logic unit being formed so as to operate on the first input, the second input and the third input by means of arithmetic sub-operations, while considering the type of encryption of the operands, such that at the output, an encrypted result is obtained which equals a value that would be obtained if the first operand was subjected to the arithmetic operation in a non-encrypted state and if the second operand would be subjected to the arithmetic operation in a non-encrypted state, and a result obtained was subsequently encrypted, no decryption of the operands being performed in the arithmetic-logic unit. In this manner, a processor system may be obtained in which no data whatsoever occurs in clear text, i.e. in a non-encrypted form, since no decryption upstream of an arithmetic-logic unit and no encryption downstream of the arithmetic-logic unit are required, as the arithmetic-logic unit operates with encrypted input operands to obtain an encrypted result. Interception attacks on transmission lines of the calculating unit are thus ruled out.

    摘要翻译: 一种计算单元,用于利用至少两个操作数执行算术运算,所述至少两个操作数被加密,包括具有用于第一加密操作数的第一输入,第二加密操作数的第二输入和第三输入的算术逻辑单元 对于加密参数和用于操作的加密结果的输出,算术逻辑单元被形成为通过算术子操作在第一输入,第二输入和第三输入上操作,同时考虑类型 使得在输出处获得加密结果,该加密结果等于如果第一操作数在非加密状态下经受算术运算而获得的值,并且如果第二操作数将受到 在未加密状态下的算术运算以及所获得的结果随后被加密,在算术逻辑单元中不执行操作数的解密。 以这种方式,可以获得处理器系统,其中无任何数据以明文形式出现,即以非加密形式出现,因为不需要算术逻辑单元上游的解密,并且不需要算术逻辑单元下游的加密 因为算术逻辑单元用加密的输入操作数操作以获得加密的结果。 因此排除了对计算单元的传输线的拦截攻击。

    Device and method for determining a physical address from a virtual address, using a hierarchical mapping rule comprising compressed nodes
    64.
    发明申请
    Device and method for determining a physical address from a virtual address, using a hierarchical mapping rule comprising compressed nodes 有权
    用于使用包括压缩节点的分层映射规则从虚拟地址确定物理地址的设备和方法

    公开(公告)号:US20050015378A1

    公开(公告)日:2005-01-20

    申请号:US10480081

    申请日:2002-05-14

    IPC分类号: G06F12/1009 G06F7/00

    摘要: A method for determining a physical address from a virtual address, wherein a mapping regulation between the virtual address and the physical address is implemented as hierarchical tree structure with compressed nodes. First, a compression indicator included in the mapping regulation is read, and a portion of the virtual address associated with the considered node level is read. Using the compression indicator and the portion of the virtual address, an entry in the node list of the considered node is determined. The determined entry is read, whereupon the physical address can be determined directly, if the considered node level has been the hierarchically lowest node level. If higher node levels to be processed are present, the previous steps in determining the physical address for compressed nodes of lower hierarchy level are repeated until the hierarchically lowest node level is reached.

    摘要翻译: 一种用于从虚拟地址确定物理地址的方法,其中虚拟地址和物理地址之间的映射调节被实现为具有压缩节点的分层树结构。 首先,读取包含在映射规则中的压缩指示符,并且读取与所考虑的节点级别相关联的虚拟地址的一部分。 使用压缩指示符和虚拟地址的一部分,确定所考虑节点的节点列表中的条目。 读取确定的条目,从而可以直接确定物理地址,如果所考虑的节点级别是层次最低的节点级别。 如果存在要处理的较高节点级别,则重复确定较低层次级别的压缩节点的物理地址的先前步骤,直到达到分级最低节点级别。

    Electronic device with a programmable resistive element and a method for blocking a device
    65.
    发明授权
    Electronic device with a programmable resistive element and a method for blocking a device 有权
    具有可编程电阻元件的电子设备和用于阻止设备的方法

    公开(公告)号:US09070439B2

    公开(公告)日:2015-06-30

    申请号:US13426019

    申请日:2012-03-21

    IPC分类号: G11C11/00 G11C13/00

    摘要: One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state.

    摘要翻译: 一个或多个实施例涉及包括电路和可编程电阻元件的电子设备。 可编程电阻元件包括第一和第二状态,其中可编程电阻元件被配置为允许响应于包括至少预定义电平的信号从第二状态切换到第一状态。 该电路被配置为提供上述预定义电平的信号,其中电路被配置为向可编程电阻元件提供开关信号,其中开关信号引起从第一状态切换到第二状态。

    Apparatus for generating a checksum
    67.
    发明授权
    Apparatus for generating a checksum 有权
    用于产生校验和的设备

    公开(公告)号:US08612842B2

    公开(公告)日:2013-12-17

    申请号:US13115382

    申请日:2011-05-25

    申请人: Berndt Gammel

    发明人: Berndt Gammel

    IPC分类号: G06F11/10 H03M13/00

    摘要: An apparatus generates a checksum for a payload having a number of payload symbols. The apparatus includes a coder for coding the payload. The coder is configured to combine a current payload symbol and a previous coding symbol or an initialization symbol to obtain a combined symbol, and map the combined symbol using a mapping rule to obtain a current coding symbol. The mapping rule is based on a power of two or more of a companion matrix of a characteristic polynomial of a linear feedback shift register. The apparatus is configured such that the checksum corresponds to the current coding symbol, when the number of payload symbols is processed by the coder, the number being one or greater than one.

    摘要翻译: 装置为具有多个有效载荷符号的有效载荷生成校验和。 该装置包括用于对有效载荷进行编码的编码器。 编码器被配置为组合当前有效载荷符号和先前编码符号或初始化符号以获得组合符号,并且使用映射规则映射组合符号以获得当前编码符号。 映射规则基于线性反馈移位寄存器的特征多项式的伴随矩阵的两个或更多个的幂。 该装置被配置为使得当编码器处理有效载荷符号的数量时,校验和对应于当前编码符号,该数目为1个或大于1个。

    Signature Update by Code Transformation
    68.
    发明申请
    Signature Update by Code Transformation 有权
    通过代码转换签名更新

    公开(公告)号:US20120246452A1

    公开(公告)日:2012-09-27

    申请号:US13428589

    申请日:2012-03-23

    IPC分类号: G06F9/318

    CPC分类号: G06F11/1004 G06F11/28

    摘要: Embodiments described herein provide an apparatus, computer readable digital storage medium and method for producing an instruction sequence for a computation unit which can be controlled by a program which includes at least the instruction sequence.

    摘要翻译: 本文描述的实施例提供了一种用于产生可由至少包括指令序列的程序控制的用于计算单元的指令序列的装置,计算机可读数字存储介质和方法。

    ELECTRONIC DEVICE WITH A PROGRAMMABLE RESISTIVE ELEMENT AND A METHOD FOR BLOCKING A DEVICE
    69.
    发明申请
    ELECTRONIC DEVICE WITH A PROGRAMMABLE RESISTIVE ELEMENT AND A METHOD FOR BLOCKING A DEVICE 审中-公开
    具有可编程电阻元件的电子设备和用于阻塞器件的方法

    公开(公告)号:US20120176833A1

    公开(公告)日:2012-07-12

    申请号:US13426019

    申请日:2012-03-21

    IPC分类号: G11C11/00

    摘要: One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state.

    摘要翻译: 一个或多个实施例涉及包括电路和可编程电阻元件的电子设备。 可编程电阻元件包括第一和第二状态,其中可编程电阻元件被配置为允许响应于包括至少预定义电平的信号从第二状态切换到第一状态。 该电路被配置为提供上述预定义电平的信号,其中电路被配置为向可编程电阻元件提供开关信号,其中开关信号引起从第一状态切换到第二状态。

    GENERATING A SESSION KEY FOR AUTHENTICATION AND SECURE DATA TRANSFER
    70.
    发明申请
    GENERATING A SESSION KEY FOR AUTHENTICATION AND SECURE DATA TRANSFER 有权
    生成用于认证和安全数据传输的会话密钥

    公开(公告)号:US20100316217A1

    公开(公告)日:2010-12-16

    申请号:US12797704

    申请日:2010-06-10

    IPC分类号: H04L9/00

    摘要: A device for generating a session key which is known to a first communication partner and a second communication partner, for the first communication partner, from secret information which may be determined by the first and second communication partners, includes a first module operable to calculate the session key using a concatenation of at least a part of a random number and a part of the secret information. The device also includes a second module operable to use the session key for communication with the second communication partner.

    摘要翻译: 从第一和第二通信伙伴可以确定的秘密信息中,生成用于第一通信对方的第一通信伙伴和第二通信伙伴知道的会话密钥的设备包括可操作以计算 会话密钥使用随机数字和秘密信息的一部分的至少一部分的级联。 该设备还包括可操作以使用会话密钥与第二通信伙伴进行通信的第二模块。